Features

• Ten single ended LVCMOS/LVTTL outputs,

7 typical output impedance

• LVPECL clock input pair

• PCLK/nPCLK supports the following input levels:

LVPECL, CML, SSTL

• Maximum input frequency: 250MHz

• Output skew: 120ps (maximum)

• Part-to-part skew: 700ps (maximum)

• Multiple frequency skew: 320ps (maximum)

• Additive phase jitter, RMS: 0.19ps (typical)

• 3.3V core, 3.3V or 2.5V output supply modes-40°C to 85°C

ambient operating temperature

• Available in lead-free (RoHS 6) package

• For functional replacement use 87946i-147