1:5, Differential-to-3.3V LVPECL Zero Delay Clock Generator

Features • Five differential 3.3V LVPECL output pairs • Selectable differential clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output frequency range: 15.625MHz to 350MHz • Input frequency range: 15.625MHz to 350MHz • V

1:5, Differential-to-3.3V LVPECL Zero Delay Clock Generator

Features • Five differential 3.3V LVPECL output pairs • Selectable differential clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output frequency range: 15.625MHz to 350MHz • Input frequency range: 15.625MHz to 350MHz • V

1:5, Differential-to-3.3V LVPECL Zero Delay Clock Generator

Features • Five differential 3.3V LVPECL output pairs • Selectable differential clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output frequency range: 15.625MHz to 350MHz • Input frequency range: 15.625MHz to 350MHz • V

1:5, Differential-to-3.3V LVPECL Zero Delay Clock Generator

Features • Five differential 3.3V LVPECL output pairs • Selectable differential clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output frequency range: 15.625MHz to 350MHz • Input frequency range: 15.625MHz to 350MHz • V

1:5, Differential-to-3.3V LVPECL Zero Delay Clock Generator

文件：424.09 Kbytes Page：21 Pages

封装/外壳：32-LQFP 包装：托盘 描述：IC CLK GEN ZD DIFF-LVPECL 32LQFP 集成电路（IC） 时钟发生器，PLL，频率合成器

1:5, Differential-to-3.3V LVPECL Zero Delay Clock Generator

文件：424.09 Kbytes Page：21 Pages

封装/外壳：32-LQFP 包装：卷带（TR） 描述：IC CLK GEN ZD 1:5 LVPECL 32-LQFP 集成电路（IC） 时钟发生器，PLL，频率合成器