丝印代码：ICS87322BYILF；Low Skew, ÷1/÷2, 3.3V LVPECL/ECL Clock Generator

FEATURES • Fifteen differential LVPECL outputs • Selectable LVPECL differential clock inputs • CLK0, nCLK0 and CLK1, nCLK1 can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Output frequency: 750MHz (maximum) • Output skew: 180ps (maximum) • Bank skew: 65ps (maxi

封装/外壳：52-LQFP 包装：托盘 描述：CLOCK GENERATORS \u0026 SUPPORT PRODU 集成电路（IC） 时钟发生器，PLL，频率合成器

丝印代码：ICS87322BYILF；Low Skew, ÷1/÷2, 3.3V LVPECL/ECL Clock Generator

FEATURES • Fifteen differential LVPECL outputs • Selectable LVPECL differential clock inputs • CLK0, nCLK0 and CLK1, nCLK1 can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Output frequency: 750MHz (maximum) • Output skew: 180ps (maximum) • Bank skew: 65ps (maxi

封装/外壳：52-LQFP 包装：卷带（TR） 描述：IC CLK GEN 15 LVPECL OTPT 52LQFP 集成电路（IC） 时钟发生器，PLL，频率合成器

Low Skew, ÷1/÷2, 3.3V LVPECL/ECL Clock Generator

FEATURES • Fifteen differential LVPECL outputs • Selectable LVPECL differential clock inputs • CLK0, nCLK0 and CLK1, nCLK1 can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Output frequency: 750MHz (maximum) • Output skew: 180ps (maximum) • Bank skew: 65ps (maxi

Dual High-Current Buck Converter and Dual Linear Regulator

文件：3.65375 Mbytes Page：75 Pages

Floppy Disk Controller with Dual UARTs, Enhanced Parallel Port, and IDE Interface

文件：1.02214 Mbytes Page：84 Pages