Low Skew, ÷1/÷2, 3.3V LVPECL/ECL Clock Generator

FEATURES • Fifteen differential LVPECL outputs • Selectable LVPECL differential clock inputs • CLK0, nCLK0 and CLK1, nCLK1 can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Output frequency: 750MHz (maximum) • Output skew: 180ps (maximum) • Bank skew: 65ps (maxi

Low Skew, ÷1/÷2,3.3V LVPECL /ECLClock Generator

The 87322BI is a low skew, ÷1/÷2 3.3V LVPECL/ECL Clock Generator. Using multiplexed/redundant clock inputs the 87322BI is designed to translate most differential signal levels to LVPECL/ECL levels. The CLK_SEL input selects between CLK0, nCLK0 and CLK1, nCLK1 as the active input. The divide select i ·Fifteen differential LVPECL outputs\n·Selectable LVPECL differential clock inputs\n·CLK0, nCLK0 and CLK1, nCLK1 can accept the following differential input levels: LVPECL, LVDS, CML, SSTL\n·Output frequency: 750MHz (maximum)\n·Output skew: 180ps (maximum)\n·Bank skew: 65ps (maximum)\n·Part-to-part ;

丝印代码：ICS87322BYILF；Low Skew, ÷1/÷2, 3.3V LVPECL/ECL Clock Generator

FEATURES • Fifteen differential LVPECL outputs • Selectable LVPECL differential clock inputs • CLK0, nCLK0 and CLK1, nCLK1 can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Output frequency: 750MHz (maximum) • Output skew: 180ps (maximum) • Bank skew: 65ps (maxi

丝印代码：ICS87322BYILF；Low Skew, ÷1/÷2, 3.3V LVPECL/ECL Clock Generator

FEATURES • Fifteen differential LVPECL outputs • Selectable LVPECL differential clock inputs • CLK0, nCLK0 and CLK1, nCLK1 can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Output frequency: 750MHz (maximum) • Output skew: 180ps (maximum) • Bank skew: 65ps (maxi

Dual High-Current Buck Converter and Dual Linear Regulator

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Floppy Disk Controller with Dual UARTs, Enhanced Parallel Port, and IDE Interface

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