Zero Delay, Differential-to-LVCMOS/ LVTTL Clock Generator

FEATURES • Eight LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • CLK0 input accepts LVCMOS or LVTTL input levels • Output frequenc

CAPTIVE PANEL SCREWS

文件：395.93 Kbytes Page：1 Pages

Zero Delay, Differential-to-LVCMOS/ LVTTL Clock Generator

FEATURES • Eight LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • CLK0 input accepts LVCMOS or LVTTL input levels • Output frequenc

封装/外壳：32-LQFP 包装：卷带（TR） 描述：IC CLOCK GENERATOR ZD 32-LQFP 集成电路（IC） 时钟发生器，PLL，频率合成器

ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

文件：183.45 Kbytes Page：18 Pages

ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

文件：183.45 Kbytes Page：18 Pages