4:1 or 2:1 LVDS Clock Multiplexer with Internal Input Termination

Features • High speed differential multiplexer. The device can be configured as either a 4:1 or 2:1 multiplexer • One LVDS output pair • Four selectable PCLK, nPCLK inputs with internal termination • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, S

4:1 or 2:1 LVDS Clock Multiplexer with Internal Input Termination

Features • High speed differential multiplexer. The device can be configured as either a 4:1 or 2:1 multiplexer • One LVDS output pair • Four selectable PCLK, nPCLK inputs with internal termination • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, S

4:1 or 2:1 LVDS Clock Multiplexer with Internal Input Termination

Features • High speed differential multiplexer. The device can be configured as either a 4:1 or 2:1 multiplexer • One LVDS output pair • Four selectable PCLK, nPCLK inputs with internal termination • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, S

4:1 or 2:1 LVDS Clock Multiplexer with Internal Input Termination

Features • High speed differential multiplexer. The device can be configured as either a 4:1 or 2:1 multiplexer • One LVDS output pair • Four selectable PCLK, nPCLK inputs with internal termination • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, S

4:1 or 2:1 LVDS Clock Multiplexer with Internal Input Termination

Features • High speed differential multiplexer. The device can be configured as either a 4:1 or 2:1 multiplexer • One LVDS output pair • Four selectable PCLK, nPCLK inputs with internal termination • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, S

4:1 or 2:1 LVDS Clock Multiplexer with Internal Input Termination

Features • High speed differential multiplexer. The device can be configured as either a 4:1 or 2:1 multiplexer • One LVDS output pair • Four selectable PCLK, nPCLK inputs with internal termination • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, S

封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 包装：托盘 描述：IC CLK MULTIPLX 4:1 2GHZ 20TSSOP 集成电路（IC） 时钟缓冲器，驱动器

4:1 or 2:1 LVDS Clock Multiplexer with Internal Input Termination

文件：532.62 Kbytes Page：15 Pages

4:1 or 2:1 LVDS Clock Multiplexer with Internal Input Termination

文件：532.62 Kbytes Page：15 Pages

封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC CLK MULTIPLX 4:1 2GHZ 20TSSOP 集成电路（IC） 时钟缓冲器，驱动器

4:1 or 2:1 LVDS Clock Multiplexer with Internal Input Termination

文件：532.62 Kbytes Page：15 Pages