Dual LVCMOS / LVTTL-TO-Differential LVHSTL Translator

FEATURES • 2 differential LVHSTL outputs • Selectable CLK0, CLK1 LVCMOS clock inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz • Part-to-part skew: 350ps (maximum) • Propagation delay: 1.3ns (maximum) • VOH: 1.2V (maximum) •

包装：散装 描述：WR RAT REV S 10MMX12MM 工具 扳手

Dual LVCMOS / LVTTL-TO-Differential

文件：152.67 Kbytes Page：13 Pages

Dual LVCMOS / LVTTL-to-Differential HSTL Translator

FEATURES • Two differential HSTL outputs • CLK0, CLK1 LVCMOS/LVTTL clock inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz • Part-to-part skew: 375ps (maximum) • Propagation delay: 1075ps (maximum) • VOH: 1.4V (maximum) • Full

1-to-2, LVCMOS/LVTTL-to-Differential HSTL Translator

FEATURES • Two differential HSTL outputs • One LVCMOS/LVTTL clock input • CLK input can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz • Part-to-part skew: 250ps (maximum) • Propagation delay: 1.25ns (maximum) • V OH : 1.4V (maximum) • Output crossov

1-TO-2 LVCMOS / LVTTL-TO DIFFERENTIAL HSTL TRANSLATOR

GENERAL DESCRIPTION The ICS85222-02 is a 1-to-2 LVCMOS / LVTTL-to-Differential HSTL translator and a member of the HiPerClocks™ family of High Performance Clock Solutions from ICS. The ICS85222-02 has one single ended clock input. The single ended clock input accepts LVCMOS or LVTTL input levels

Dual LVCMOS / LVTTL-to-Differential HSTL Translator

FEATURES • Two differential HSTL outputs • CLK0, CLK1 LVCMOS/LVTTL clock inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz • Part-to-part skew: 375ps (maximum) • Propagation delay: 1075ps (maximum) • VOH: 1.4V (maximum) • Full

Dual LVCMOS / LVTTL-to-Differential HSTL Translator

FEATURES • Two differential HSTL outputs • CLK0, CLK1 LVCMOS/LVTTL clock inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz • Part-to-part skew: 375ps (maximum) • Propagation delay: 1075ps (maximum) • VOH: 1.4V (maximum) • Full

Dual LVCMOS / LVTTL-TO-Differential LVHSTL Translator

FEATURES • 2 differential LVHSTL outputs • Selectable CLK0, CLK1 LVCMOS clock inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz • Part-to-part skew: 350ps (maximum) • Propagation delay: 1.3ns (maximum) • VOH: 1.2V (maximum) •

Dual LVCMOS / LVTTL-TO-Differential LVHSTL Translator

FEATURES • 2 differential LVHSTL outputs • Selectable CLK0, CLK1 LVCMOS clock inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz • Part-to-part skew: 350ps (maximum) • Propagation delay: 1.3ns (maximum) • VOH: 1.2V (maximum) •

Dual LVCMOS / LVTTL-to-Differential HSTL Translator

文件：184.46 Kbytes Page：14 Pages

1-to-2, LVCMOS/LVTTL-to-Differential HSTL Translator

文件：211.53 Kbytes Page：12 Pages

包装：盒 描述：E-J MK-II(+) 15P CAP DBL

Dual LVCMOS / LVTTL-to-Differential HSTL Translator

文件：184.46 Kbytes Page：14 Pages

Dual LVCMOS / LVTTL-to-Differential HSTL Translator

文件：184.46 Kbytes Page：14 Pages

Dual LVCMOS / LVTTL-TO-Differential

文件：152.67 Kbytes Page：13 Pages

Dual LVCMOS / LVTTL-TO-Differential

文件：152.67 Kbytes Page：13 Pages