丝印代码：ICS30S07AIL；Clock Generator for Cavium Processors

Features • One selectable differential LVPECL output pair for DDR 533/400/667 • Six LVCMOS/ LVTTL outputs, 15Ω typical output impedance - One selectable core clock for the processor - One selectable clock for the PCI/ PCI-X bus - One 125MHz clock reference for GbE MAC - Three 25MHz clock re

丝印代码：ICS30S07AIL；Clock Generator for Cavium Processors

Features • One selectable differential LVPECL output pair for DDR 533/400/667 • Six LVCMOS/ LVTTL outputs, 15Ω typical output impedance - One selectable core clock for the processor - One selectable clock for the PCI/ PCI-X bus - One 125MHz clock reference for GbE MAC - Three 25MHz clock re

Clock Generator for Cavium Processors

文件：885.75 Kbytes Page：26 Pages

Clock Generator for Cavium Processors

文件：885.75 Kbytes Page：26 Pages

Clock Generator for Cavium Processors

Features • One selectable differential LVPECL output pair for DDR 533/400/667 • Six LVCMOS/ LVTTL outputs, 15Ω typical output impedance - One selectable core clock for the processor - One selectable clock for the PCI/ PCI-X bus - One 125MHz clock reference for GbE MAC - Three 25MHz clock re