封装/外壳：56-BSSOP（0.295"，7.50mm 宽） 包装：管件 描述：IC PLL WAN 51/E1/OC3 DUAL 56SSOP 集成电路（IC） 应用特定时钟/定时

封装/外壳：56-BSSOP（0.295"，7.50mm 宽） 包装：卷带（TR） 描述：IC PLL WAN 51/E1/OC3 DUAL 56SSOP 集成电路（IC） 应用特定时钟/定时

T1/E1/OC3 TELECOM CLOCK GENERATOR WITH DUAL REFERENCE INPUTS

DESCRIPTION The IDT82V3010 is a T1/E1/OC3 telecom clock generator with dual reference inputs. It contains a Digital Phase-Locked Loop (DPLL), which generates low jitter ST-BUS and 19.44 MHz clock and framing signals that are phase locked to an 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz input r

T1/E1/OC3 TELECOM CLOCK GENERATOR WITH DUAL REFERENCE INPUTS

FEATURES • Supports AT&T TR62411 • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface • Selectable reference inputs: 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz • Accepts two independent reference inputs which may have same or different nominal frequencies applied to t

T1/E1/OC3 TELECOM CLOCK GENERATOR WITH DUAL REFERENCE INPUTS

DESCRIPTION The IDT82V3010 is a T1/E1/OC3 telecom clock generator with dual reference inputs. It contains a Digital Phase-Locked Loop (DPLL), which generates low jitter ST-BUS and 19.44 MHz clock and framing signals that are phase locked to an 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz input r

T1/E1/OC3 TELECOM CLOCK GENERATOR WITH DUAL REFERENCE INPUTS

DESCRIPTION The IDT82V3010 is a T1/E1/OC3 telecom clock generator with dual reference inputs. It contains a Digital Phase-Locked Loop (DPLL), which generates low jitter ST-BUS and 19.44 MHz clock and framing signals that are phase locked to an 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz input r

T1/E1/OC3 TELECOM CLOCK GENERATOR WITH DUAL REFERENCE INPUTS

FEATURES • Supports AT&T TR62411 • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface • Selectable reference inputs: 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz • Accepts two independent reference inputs which may have same or different nominal frequencies applied to t