Octal D-type flip-flop with data enable; positive-edge trigger

DESCRIPTION The 74LVC377 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Conforms to JEDEC standard 8-1A • Inputs accept voltages up to 5.5V • CMOS low power consumption • Direct interface w

Octal D-type flip-flop with data enable; positive-edge trigger

1. General description The 74LVC377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-

Octal D-type flip-flop with data enable; positive-edge trigger

1. General description The 74LVC377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-

Octal D-type flip-flop with data enable; positive-edge trigger

DESCRIPTION The 74LVC377 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Conforms to JEDEC standard 8-1A • Inputs accept voltages up to 5.5V • CMOS low power consumption • Direct interface w

Octal D-type flip-flop with data enable; positive-edge trigger

DESCRIPTION The 74LVC377 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Conforms to JEDEC standard 8-1A • Inputs accept voltages up to 5.5V • CMOS low power consumption • Direct interface w