Octal D-type flip-flop with data enable; positive-edge trigger

DESCRIPTION The 74LVC377 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Conforms to JEDEC standard 8-1A • Inputs accept voltages up to 5.5V • CMOS low power consumption • Direct interface w

Octal D-type flip-flop with data enable; positive-edge trigger

1. General description The 74LVC377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-

Octal D-type flip-flop with data enable; positive-edge trigger

The 74LVC377 has eight edge-triggered D-type flip-flops with individual inputs (D) and outputs (Q). A common clock input (CP) loads all flip-flops simultaneously when data enable input (E) is LOW. The state of each D input, one set-up time before the LOW to HIGH clock transition, is transferred to t • Wide supply voltage range from 1.2 V to 3.6 V\n• Inputs accept voltages up to 5.5 V\n• CMOS low power consumption\n• Direct interface with TTL levels\n• Output drive capability 50 Ω transmission lines at 125 °C\n• Complies with JEDEC standard:• JESD8-7A (1.65 V to 1.95 V)\n• JESD8-5A (2.3 V to 2.7;

Octal D-type flip-flop with data enable; positive-edge trigger

The 74LVC377 has eight edge-triggered D-type flip-flops with individual inputs (D) and outputs (Q). A common clock input (CP) loads all flip-flops simultaneously when data enable input (E) is LOW. The state of each D input, one set-up time before the LOW to HIGH clock transition, is transferred to t • Wide supply voltage range from 1.2 V to 3.6 V\n• Inputs accept voltages up to 5.5 V\n• CMOS low power consumption\n• Direct interface with TTL levels\n• Output drive capability 50 Ω transmission lines at 125 °C\n• Complies with JEDEC standard:• JESD8-7A (1.65 V to 1.95 V)\n• JESD8-5A (2.3 V to 2.7;

Octal D-type flip-flop with data enable; positive-edge trigger

DESCRIPTION The 74LVC377 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Conforms to JEDEC standard 8-1A • Inputs accept voltages up to 5.5V • CMOS low power consumption • Direct interface w

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 功能：标准 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE SNGL 8BIT 20SO 集成电路（IC） 触发器

封装/外壳：20-SSOP（0.209"，5.30mm 宽） 功能：标准 包装：卷带（TR） 描述：IC FF D-TYPE SNGL 8BIT 20SSOP 集成电路（IC） 触发器

Octal D-type flip-flop with data enable; positive-edge trigger

DESCRIPTION The 74LVC377 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Conforms to JEDEC standard 8-1A • Inputs accept voltages up to 5.5V • CMOS low power consumption • Direct interface w

Octal D-type flip-flop with data enable; positive-edge trigger

DESCRIPTION The 74LVC377 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Conforms to JEDEC standard 8-1A • Inputs accept voltages up to 5.5V • CMOS low power consumption • Direct interface w

3.3V CMOS 8-BIT REGISTER WITH CLOCK ENABLE AND 5 VOLT TOLERANT I/O

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