Single Schmitt-trigger buffer

DESCRIPTION The 74LVC1G17 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

Single Schmitt trigger buffer

SINGLE SCHMITT-TRIGGER BUFFER

Description The 74LVC1G17 is a single 1-input Schmitt-trigger buffer with a standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is ful

Single Schmitt trigger buffer

1. General description The 74LVC1G17 is a single buffer Schmitt-trigger. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. This device is fully specified for partial power down applications usi

SINGLE SCHMITT-TRIGGER BUFFER

Features * Operation Voltage Range: 1.65V ~ 5.5V. « Low power current Icc=10pA(Max) « £24mA output dive (Voc=3.0V) « Power down protection * ESD Protection Exceeds JESD 22 = 2000-V Human-Body Model (A114-A) ~1000-V Charged-Device Model (C101) * SOT23-5 Package Available « SOT353 Package A

Single Schmitt-Trigger Buffer

Single-gate

Single Schmitt trigger buffer

SINGLE SCHMITT-TRIGGER BUFFER

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Single D-type flip-flop with reset; positive-edge trigger

Single D-type flip-flop with reset; positive-edge trigger

General description The 74LVC1G175 is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Th

Single D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the

SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear

1 Features 1• Available in the Texas Instruments NanoFree™ Package • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Supports Down Translation to VCC • Max tpd of 4.3 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff Supports Live Inse

SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear

1 Features 1• Available in the Texas Instruments NanoFree™ Package • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Supports Down Translation to VCC • Max tpd of 4.3 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff Supports Live Inse

SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear

1 Features 1• Available in the Texas Instruments NanoFree™ Package • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Supports Down Translation to VCC • Max tpd of 4.3 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff Supports Live Inse

SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear

1 Features 1• Available in the Texas Instruments NanoFree™ Package • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Supports Down Translation to VCC • Max tpd of 4.3 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff Supports Live Inse

SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear

1 Features 1• Available in the Texas Instruments NanoFree™ Package • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Supports Down Translation to VCC • Max tpd of 4.3 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff Supports Live Inse

SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear

1 Features 1• Available in the Texas Instruments NanoFree™ Package • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Supports Down Translation to VCC • Max tpd of 4.3 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff Supports Live Inse

SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear

1 Features 1• Available in the Texas Instruments NanoFree™ Package • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Supports Down Translation to VCC • Max tpd of 4.3 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff Supports Live Inse

SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear

1 Features 1• Available in the Texas Instruments NanoFree™ Package • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Supports Down Translation to VCC • Max tpd of 4.3 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff Supports Live Inse

SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear

1 Features 1• Available in the Texas Instruments NanoFree™ Package • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Supports Down Translation to VCC • Max tpd of 4.3 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff Supports Live Inse

SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear

1 Features 1• Available in the Texas Instruments NanoFree™ Package • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Supports Down Translation to VCC • Max tpd of 4.3 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff Supports Live Inse

SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear

1 Features 1• Available in the Texas Instruments NanoFree™ Package • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Supports Down Translation to VCC • Max tpd of 4.3 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff Supports Live Inse

SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear

1 Features 1• Available in the Texas Instruments NanoFree™ Package • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Supports Down Translation to VCC • Max tpd of 4.3 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff Supports Live Inse

SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear

1 Features 1• Available in the Texas Instruments NanoFree™ Package • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Supports Down Translation to VCC • Max tpd of 4.3 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff Supports Live Inse

SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear

1 Features 1• Available in the Texas Instruments NanoFree™ Package • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Supports Down Translation to VCC • Max tpd of 4.3 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff Supports Live Inse

Single D-type flip-flop with reset; positive-edge trigger

Single D-type flip-flop with reset; positive-edge trigger

Single D-type flip-flop with reset; positive-edge trigger

General description The 74LVC1G175 is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Th

Single D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the

Single D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the

Single D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the

Single D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the

Single D-type flip-flop with reset; positive-edge trigger

Single D-type flip-flop with reset; positive-edge trigger

General description The 74LVC1G175 is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Th

Single D-type flip-flop with reset; positive-edge trigger

Single D-type flip-flop with reset; positive-edge trigger

General description The 74LVC1G175 is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Th

Single D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the

SINGLE SCHMITT-TRIGGER BUFFER

Description The 74LVC1G17 is a single 1-input Schmitt-trigger buffer with a standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is ful

SINGLE SCHMITT-TRIGGER BUFFER

Description The 74LVC1G17 is a single 1-input Schmitt-trigger buffer with a standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is ful

SINGLE SCHMITT-TRIGGER BUFFER

Description The 74LVC1G17 is a single 1-input Schmitt-trigger buffer with a standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is ful

SINGLE SCHMITT-TRIGGER BUFFER

Description The 74LVC1G17 is a single 1-input Schmitt-trigger buffer with a standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is ful

Single Schmitt trigger buffer

Single Schmitt trigger buffer

Single Schmitt trigger buffer

Single Schmitt-trigger buffer

DESCRIPTION The 74LVC1G17 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

Single Schmitt trigger buffer

Single Schmitt trigger buffer

1. General description The 74LVC1G17 is a single buffer Schmitt-trigger. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. This device is fully specified for partial power down applications usi

Single Schmitt trigger buffer

1. General description The 74LVC1G17-Q100 is a single buffer Schmitt-trigger. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. This device is fully specified for partial power down application

Single Schmitt trigger buffer

1. General description The 74LVC1G17-Q100 is a single buffer Schmitt-trigger. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. This device is fully specified for partial power down application

Single Schmitt trigger buffer

Single Schmitt trigger buffer

1. General description The 74LVC1G17 is a single buffer Schmitt-trigger. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. This device is fully specified for partial power down applications usi

Single Schmitt trigger buffer

1. General description The 74LVC1G17 is a single buffer Schmitt-trigger. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. This device is fully specified for partial power down applications usi

Single Schmitt trigger buffer

Single Schmitt trigger buffer

Single Schmitt trigger buffer

Single Schmitt-trigger buffer

DESCRIPTION The 74LVC1G17 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

Single Schmitt trigger buffer

1. General description The 74LVC1G17 is a single buffer Schmitt-trigger. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. This device is fully specified for partial power down applications usi

Single Schmitt trigger buffer

1. General description The 74LVC1G17-Q100 is a single buffer Schmitt-trigger. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. This device is fully specified for partial power down application

Single Schmitt trigger buffer

1. General description The 74LVC1G17-Q100 is a single buffer Schmitt-trigger. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. This device is fully specified for partial power down application