1. General description

The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with

individual data (D) input, clock (CP) input, master reset (MR) input, and Q output.

The master reset (MR) is an asynchronous active LOW input and operates independently of the

clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH

transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH

clock transition for predictable operation.

The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device

in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry

disables the output, preventing the damaging backflow current through the device when it is

powered down.

Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall

times.

2. Features and benefits

• Wide supply voltage range from 1.65 V to 5.5 V

• High noise immunity

• Overvoltage tolerant inputs to 5.5 V

• ±24 mA output drive (VCC = 3.0 V)

• CMOS low power dissipation

• Direct interface with TTL levels

• IOFF circuitry provides partial Power-down mode operation

• Latch-up performance exceeds 250 mA

• Complies with JEDEC standard:

• JESD8-7 (1.65 V to 1.95 V)

• JESD8-5 (2.3 V to 2.7 V)

• JESD8C (2.7 V to 3.6 V)

• JESD36 (4.5 V to 5.5 V)

• ESD protection:

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V.

• Multiple package options

• Specified from -40 °C to +85 °C and -40 °C to +125 °C.