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74HCT74价格
参考价格：￥0.3560
型号：74HCT74D,652 品牌：NXP 备注：这里有74HCT74多少钱，2025年最近7天走势，今日出价，今日竞价，74HCT74批发/采购报价，74HCT74行情走势销售排行榜，74HCT74报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
74HCT74 | Dual D-type flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: flip-flops | Philips 飞利浦 |   | |
74HCT74 | Dual D-type flip-flop with set and reset; positive edge-trigger 1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW- | NEXPERIA 安世 | | |
74HCT74 | Dual D-type flip-flop with set and reset; positive edge-trigger | ETC 知名厂家 | ETC | |
74HCT74 | Dual D-type flip-flop with set and reset; positive edge-trigger | ETC 知名厂家 | ETC | |
74HCT74 | Dual D-type flip-flop with set and reset; positive edge-trigger 文件：175.47 Kbytes Page：21 Pages | Philips 飞利浦 | | |
4-Bit x 64-word FIFO register; 3-state GENERAL DESCRIPTION The 74HC/HCT7403 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no.7A. FEATURES • Synchronous or asynchronous operation • 3-state outputs • 30 MHz (typical) shift-in and shift-out rates • Readily expandable in word | Philips 飞利浦 | | ||
4-Bit x 64-word FIFO register; 3-state GENERAL DESCRIPTION The 74HC/HCT7403 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no.7A. FEATURES • Synchronous or asynchronous operation • 3-state outputs • 30 MHz (typical) shift-in and shift-out rates • Readily expandable in word | Philips 飞利浦 | | ||
4-Bit x 64-word FIFO register; 3-state GENERAL DESCRIPTION The 74HC/HCT7403 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no.7A. FEATURES • Synchronous or asynchronous operation • 3-state outputs • 30 MHz (typical) shift-in and shift-out rates • Readily expandable in word | Philips 飞利浦 | | ||
5-Bit x 64-word FIFO register; 3-state GENERAL DESCRIPTION The 74HC/HCT7404 are high-speed Si-gate CMOS devices specified in compliance with JEDEC standard no.7A. The “7404” is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 5 bits. A guaranteed 15 MHz data-rate makes it ideal for high-speed applications. | Philips 飞利浦 | | ||
5-Bit x 64-word FIFO register; 3-state GENERAL DESCRIPTION The 74HC/HCT7404 are high-speed Si-gate CMOS devices specified in compliance with JEDEC standard no.7A. The “7404” is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 5 bits. A guaranteed 15 MHz data-rate makes it ideal for high-speed applications. | Philips 飞利浦 | | ||
5-Bit x 64-word FIFO register; 3-state GENERAL DESCRIPTION The 74HC/HCT7404 are high-speed Si-gate CMOS devices specified in compliance with JEDEC standard no.7A. The “7404” is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 5 bits. A guaranteed 15 MHz data-rate makes it ideal for high-speed applications. | Philips 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger | ETC 知名厂家 | ETC | | |
Dual D-type flip-flop with set and reset; positive edge-trigger 1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW- | NEXPERIA 安世 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: flip-flops | Philips 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW- | NEXPERIA 安世 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW- | NEXPERIA 安世 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: flip-flops | Philips 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger | ETC 知名厂家 | ETC | | |
Dual D-type flip-flop with set and reset; positive edge-trigger | ETC 知名厂家 | ETC | | |
Dual D-type flip-flop with set and reset; positive edge-trigger | ETC 知名厂家 | ETC | | |
Dual D-type flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: flip-flops | Philips 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger | ETC 知名厂家 | ETC | | |
Dual D-type flip-flop with set and reset; positive edge-trigger | ETC 知名厂家 | ETC | | |
Dual D-type flip-flop with set and reset; positive edge-trigger | ETC 知名厂家 | ETC | | |
Dual D-type flip-flop with set and reset; positive edge-trigger | ETC 知名厂家 | ETC | | |
Dual D-type flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: flip-flops | Philips 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: flip-flops | Philips 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW- | NEXPERIA 安世 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger | ETC 知名厂家 | ETC | | |
封装/外壳：16-SOIC（0.295"，7.50mm 宽） 功能：异步，同步 包装：托盘 描述：IC FIFO REGISTER 64X4 3ST 16SOIC 集成电路（IC） FIFO 存储器 | ETC 知名厂家 | ETC | | |
封装/外壳：16-SOIC（0.295"，7.50mm 宽） 功能：异步，同步 包装：托盘 描述：IC FIFO REGISTER 4X64 3ST 16SOIC 集成电路（IC） FIFO 存储器 | ETC 知名厂家 | ETC | | |
4-bit x 64-word FIFO register; 3-state | ETC 知名厂家 | ETC | | |
Dual D-type flip-flop with set and reset; positive edge-trigger 文件：175.47 Kbytes Page：21 Pages | Philips 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 文件：193.4 Kbytes Page：22 Pages | Philips 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger | NEXPERIA 安世 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger | NEXPERIA 安世 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 文件：798.65 Kbytes Page：19 Pages | NEXPERIA 安世 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger | NEXPERIA 安世 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 文件：175.47 Kbytes Page：21 Pages | Philips 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 文件：193.4 Kbytes Page：22 Pages | Philips 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 文件：193.4 Kbytes Page：22 Pages | Philips 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 文件：175.47 Kbytes Page：21 Pages | Philips 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 文件：798.65 Kbytes Page：19 Pages | NEXPERIA 安世 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 文件：175.47 Kbytes Page：21 Pages | Philips 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 文件：193.4 Kbytes Page：22 Pages | Philips 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 文件：175.47 Kbytes Page：21 Pages | Philips 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 文件：193.4 Kbytes Page：22 Pages | Philips 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 文件：798.65 Kbytes Page：19 Pages | NEXPERIA 安世 | | ||
Dual D-type flip-flop with set and reset; positive edge-trigger 文件：798.65 Kbytes Page：19 Pages | NEXPERIA 安世 | |
74HCT74产品属性
- 类型
描述
- 型号
74HCT74
- 制造商
RCA
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI/德州仪器 |
24+ |
NA/ |
212 |
优势代理渠道,原装正品,可全系列订货开增值税票 |
|||
恩XP |
24+ |
标准封装 |
8448 |
全新原装正品/价格优惠/质量保障 |
|||
恩XP |
2016+ |
TSSOP14 |
2000 |
只做原装,假一罚十,公司可开17%增值税发票! |
|||
PHI |
23+ |
TSSOP |
20000 |
全新原装假一赔十 |
|||
HARRIS/哈里斯 |
25+ |
SOP-143.9mm |
65428 |
百分百原装现货 实单必成 |
|||
NEXPERIA/安世 |
25+ |
SOP |
32000 |
NEXPERIA/安世全新特价74HCT74D即刻询购立享优惠#长期有货 |
|||
PHIL |
24+/25+ |
628 |
原装正品现货库存价优 |
||||
FSC |
25+ |
DIP |
3000 |
全新原装、诚信经营、公司现货销售 |
|||
恩XP |
23+ |
贴片 |
4600 |
绝对全新原装!优势供货渠道!特价!请放心订购! |
|||
PHI |
24+ |
TSSOP14 |
25843 |
公司原厂原装现货假一罚十!特价出售!强势库存! |
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74HCT74规格书下载地址
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DdatasheetPDF页码索引
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