Dual D-type flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: flip-flops

Dual D-type flip-flop with set and reset; positive edge-trigger

Dual D-type flip-flop with set and reset; positive edge-trigger

Dual D-type flip-flop with set and reset; positive-edge trigger

The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, is • Input levels:• For 74HC74: CMOS level\n• For 74HCT74: TTL level\n\n• Symmetrical output impedance\n• Low power dissipation\n• High noise immunity\n• Balanced propagation delays\n• Specified in compliance with JEDEC standard no. 7A\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A1;

Dual D-type flip-flop with set and reset; positive edge-trigger

文件：175.47 Kbytes Page：21 Pages

Dual D-type flip-flop with set and reset; positive edge-trigger

文件：193.4 Kbytes Page：22 Pages

封装/外壳：14-SSOP（0.209"，5.30mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF D-TYPE DUAL 1BIT 14SSOP 集成电路（IC） 触发器

封装/外壳：14-SSOP（0.209"，5.30mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF D-TYPE DUAL 1BIT 14SSOP 集成电路（IC） 触发器

Dual D-type flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: flip-flops

Dual D Flip-Flop with Set and Reset with LSTTL Compatible Inputs

Dual D Flip-Flop with Set and Reset with LSTTL Compatible Inputs High–Performance Silicon–Gate CMOS The MC74HCT74A is identical in pinout to the LS74. This device may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device consists of two D flip−fl

Dual D Flip-Flop with Set and Reset with LSTTL Compatible Inputs

Dual D Flip-Flop with Set and Reset with LSTTL Compatible Inputs High–Performance Silicon–Gate CMOS The MC74HCT74A is identical in pinout to the LS74. This device may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device consists of two D flip−fl

Dual D Flip-Flop with Set and Reset with LSTTL Compatible Inputs

Dual D Flip-Flop with Set and Reset with LSTTL Compatible Inputs High–Performance Silicon–Gate CMOS The MC74HCT74A is identical in pinout to the LS74. This device may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device consists of two D flip−fl

Dual D Flip-Flop with Set and Reset with LSTTL Compatible Inputs

High–Performance Silicon–Gate CMOS The MC74HCT74A is identical in pinout to the LS74. This device may be usedas a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device consists of two D flip–flops with individual Set, Reset, and Clock inputs. Information a