Octal D-type flip-flop with data enable; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s

74HCT377DB - Octal D-type flip-flop with data enable; positive-edge trigger

Octal D-type flip-flop with data enable; positive-edge trigger - The 74HC377; 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up ·Common clock and master reset\n·Eight positive edge-triggered D-type flip-flops\n·Complies with JEDEC standard no. 7A\n·Input levels:·For 74HC377: CMOS level\n·For 74HCT377: TTL level;

Octal D-type flip-flop with data enable; positive-edge trigger

The 74HC377‑Q100; 74HCT377‑Q100 is an octal positive‑edge triggered D‑type flip‑flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW‑to‑HIGH clock (C • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40°C to +85°C and from -40°C to +125°C\n\n• Input levels:• For 74HC377-Q100: CMOS level\n• For 74HCT377-Q100: TTL level\n\n• Common clock and master reset\n• Eight positive edge-triggered D-type flip-flops\n• C;

封装/外壳：20-SSOP（0.209"，5.30mm 宽） 功能：标准 包装：管件 描述：IC FF D-TYPE SNGL 8BIT 20SSOP 集成电路（IC） 触发器

Octal D-type flip-flop with data enable; positive-edge trigger

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封装/外壳：20-SSOP（0.209"，5.30mm 宽） 功能：标准 包装：卷带（TR）剪切带（CT） 描述：IC FF D-TYPE SNGL 8BIT 20SSOP 集成电路（IC） 触发器

Octal D-type flip-flop with data enable; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s

Octal D-type flip-flop with data enable; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s

Octal D-type flip-flop with data enable; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s

Octal D-type flip-flop with data enable; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s