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74HCT377价格
参考价格：￥1.1313
型号：74HCT377D,652 品牌：NXP 备注：这里有74HCT377多少钱，2026年最近7天走势，今日出价，今日竞价，74HCT377批发/采购报价，74HCT377行情走势销售排行榜，74HCT377报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
74HCT377 | Octal D-type flip-flop with data enable; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s | PHILIPS 飞利浦 |   | |
74HCT377 | OCTAL D-TYPE FLIP-FLOP WITH DATA ENABLE POSITIVE EDGE TRIGGER OCTAL D-TYPE FLIP-FLOP WITH DATA ENABLE POSITIVE EDGE TRIGGER | ETCList of Unclassifed Manufacturers 未分类制造商 | | |
74HCT377 | Octal D-type flip-flop with data enable; positive-edge trigger 1. General description The 74HC377; 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LO | NEXPERIA 安世 | | |
Octal D-type flip-flop with data enable; positive-edge trigger 1. General description The 74HC377; 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LO | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s | PHILIPS 飞利浦 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s | PHILIPS 飞利浦 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger 1. General description The 74HC377-Q100; 74HCT377-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s | PHILIPS 飞利浦 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s | PHILIPS 飞利浦 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger 1. General description The 74HC377; 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LO | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger 1. General description The 74HC377-Q100; 74HCT377-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger 1. General description The 74HC377-Q100; 74HCT377-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements | NEXPERIA 安世 | | ||
封装/外壳：20-SOIC（0.295"，7.50mm 宽） 功能：标准 包装：管件 描述：IC FF D-TYPE SNGL 8BIT 20SO 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | | |
74HCT377DB - Octal D-type flip-flop with data enable; positive-edge trigger | NEXPERIA 安世 | | ||
封装/外壳：20-SSOP（0.209"，5.30mm 宽） 功能：标准 包装：管件 描述：IC FF D-TYPE SNGL 8BIT 20SSOP 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | | |
Octal D-type flip-flop with data enable; positive-edge trigger 文件：721.41 Kbytes Page：18 Pages | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger 文件：721.41 Kbytes Page：18 Pages | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger 文件：721.41 Kbytes Page：18 Pages | NEXPERIA 安世 | |
74HCT377产品属性
- 类型
描述
- 型号
74HCT377
- 制造商
NXP Semiconductors
- 功能描述
HCT D-Type Bus Interface Bulk
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
Nexperia |
25+ |
SSOP-20 |
21000 |
正规渠道,免费送样。支持账期,BOM一站式配齐 |
|||
恩XP |
25+ |
TSSOP20 |
1476 |
原装现货,免费供样,技术支持,原厂对接 |
|||
HAR |
23+ |
NA |
20000 |
全新原装假一赔十 |
|||
ph |
25+ |
500000 |
行业低价,代理渠道 |
||||
PHI |
TSSOP-20 |
68500 |
一级代理 原装正品假一罚十价格优势长期供货 |
||||
恩XP |
24+ |
N/A |
25843 |
公司原厂原装现货假一罚十!特价出售!强势库存! |
|||
PHI |
00+/01+ |
NULL |
2109 |
全新原装100真实现货供应 |
|||
TI |
25+ |
6 |
公司优势库存 热卖中!! |
||||
NEXPERIA/安世 |
2450+ |
NA |
9850 |
只做原厂原装正品现货或订货假一赔十! |
|||
PHI |
26+ |
原厂原装封装 |
86910 |
全新原装进口现货价格优惠 本公司承诺原装正品假一赔 |
74HCT377规格书下载地址
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DdatasheetPDF页码索引
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