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74HCT377价格
参考价格：￥1.1313
型号：74HCT377D,652 品牌：NXP 备注：这里有74HCT377多少钱，2025年最近7天走势，今日出价，今日竞价，74HCT377批发/采购报价，74HCT377行情走势销售排行榜，74HCT377报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
74HCT377 | Octal D-type flip-flop with data enable; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s | Philips 飞利浦 |   | |
74HCT377 | OCTAL D-TYPE FLIP-FLOP WITH DATA ENABLE POSITIVE EDGE TRIGGER OCTAL D-TYPE FLIP-FLOP WITH DATA ENABLE POSITIVE EDGE TRIGGER | ETCList of Unclassifed Manufacturers 未分类制造商 | | |
74HCT377 | Octal D-type flip-flop with data enable; positive-edge trigger 1. General description The 74HC377; 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LO | NEXPERIA 安世 | | |
Octal D-type flip-flop with data enable; positive-edge trigger 1. General description The 74HC377; 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LO | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s | Philips 飞利浦 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s | Philips 飞利浦 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger 1. General description The 74HC377-Q100; 74HCT377-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s | Philips 飞利浦 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s | Philips 飞利浦 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger 1. General description The 74HC377; 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LO | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger 1. General description The 74HC377-Q100; 74HCT377-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger 1. General description The 74HC377-Q100; 74HCT377-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements | NEXPERIA 安世 | | ||
封装/外壳：20-SOIC（0.295"，7.50mm 宽） 功能：标准 包装：管件 描述：IC FF D-TYPE SNGL 8BIT 20SO 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | | |
74HCT377DB - Octal D-type flip-flop with data enable; positive-edge trigger | NEXPERIA 安世 | | ||
封装/外壳：20-SSOP（0.209"，5.30mm 宽） 功能：标准 包装：管件 描述：IC FF D-TYPE SNGL 8BIT 20SSOP 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | | |
Octal D-type flip-flop with data enable; positive-edge trigger 文件：721.41 Kbytes Page：18 Pages | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger 文件：721.41 Kbytes Page：18 Pages | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger 文件：721.41 Kbytes Page：18 Pages | NEXPERIA 安世 | |
74HCT377产品属性
- 类型
描述
- 型号
74HCT377
- 制造商
NXP Semiconductors
- 功能描述
HCT D-Type Bus Interface Bulk
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
NEXPERIA/安世 |
25+ |
SOT339-1 |
600000 |
NEXPERIA/安世全新特价74HCT377DB即刻询购立享优惠#长期有排单订 |
|||
PHI |
24+/25+ |
15 |
原装正品现货库存价优 |
||||
NEXPERIA/安世 |
2450+ |
NA |
9850 |
只做原厂原装正品现货或订货假一赔十! |
|||
恩XP |
22+ |
20TSSOP |
9000 |
原厂渠道,现货配单 |
|||
PHI |
25+ |
7.2mm |
2987 |
只售原装自家现货!诚信经营!欢迎来电! |
|||
Nexperia |
23+ |
TO-18 |
12800 |
原装正品代理商最优惠价格 现货或订货 |
|||
NEXPERIA/安世 |
21+ |
NA |
12820 |
只做原装,质量保证 |
|||
PHI |
23+ |
SOP20 |
3000 |
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、 |
|||
PHI |
23+ |
NA |
9856 |
原装正品,假一罚百! |
|||
PHI |
TSSOP-20 |
68500 |
一级代理 原装正品假一罚十价格优势长期供货 |
74HCT377规格书下载地址
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DdatasheetPDF页码索引
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