74HCT377价格
参考价格：￥1.1313
型号：74HCT377D,652 品牌：NXP 备注：这里有74HCT377多少钱，2026年最近7天走势，今日出价，今日竞价，74HCT377批发/采购报价，74HCT377行情走势销售排行榜，74HCT377报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
74HCT377 | Octal D-type flip-flop with data enable; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s | PHILIPS 飞利浦 |   | |
74HCT377 | OCTAL D-TYPE FLIP-FLOP WITH DATA ENABLE POSITIVE EDGE TRIGGER OCTAL D-TYPE FLIP-FLOP WITH DATA ENABLE POSITIVE EDGE TRIGGER | ETCList of Unclassifed Manufacturers 未分类制造商 | | |
74HCT377 | Octal D-type flip-flop with data enable; positive-edge trigger 1. General description The 74HC377; 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LO | NEXPERIA 安世 | | |
Octal D-type flip-flop with data enable; positive-edge trigger 1. General description The 74HC377; 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LO | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s | PHILIPS 飞利浦 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s | PHILIPS 飞利浦 | | ||
74HCT377DB - Octal D-type flip-flop with data enable; positive-edge trigger Octal D-type flip-flop with data enable; positive-edge trigger - The 74HC377; 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up ·Common clock and master reset\n·Eight positive edge-triggered D-type flip-flops\n·Complies with JEDEC standard no. 7A\n·Input levels:·For 74HC377: CMOS level\n·For 74HCT377: TTL level; | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger The 74HC377‑Q100; 74HCT377‑Q100 is an octal positive‑edge triggered D‑type flip‑flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW‑to‑HIGH clock (C • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40°C to +85°C and from -40°C to +125°C\n\n• Input levels:• For 74HC377-Q100: CMOS level\n• For 74HCT377-Q100: TTL level\n\n• Common clock and master reset\n• Eight positive edge-triggered D-type flip-flops\n• C; | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger 1. General description The 74HC377-Q100; 74HCT377-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger The 74HC377‑Q100; 74HCT377‑Q100 is an octal positive‑edge triggered D‑type flip‑flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW‑to‑HIGH clock (C • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40°C to +85°C and from -40°C to +125°C\n\n• Input levels:• For 74HC377-Q100: CMOS level\n• For 74HCT377-Q100: TTL level\n\n• Common clock and master reset\n• Eight positive edge-triggered D-type flip-flops\n• C; | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s | PHILIPS 飞利浦 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s | PHILIPS 飞利浦 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger 1. General description The 74HC377; 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LO | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger 1. General description The 74HC377-Q100; 74HCT377-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger 1. General description The 74HC377-Q100; 74HCT377-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements | NEXPERIA 安世 | | ||
封装/外壳：20-SOIC（0.295"，7.50mm 宽） 功能：标准 包装：管件 描述：IC FF D-TYPE SNGL 8BIT 20SO 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | | |
封装/外壳：20-SSOP（0.209"，5.30mm 宽） 功能：标准 包装：管件 描述：IC FF D-TYPE SNGL 8BIT 20SSOP 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | | |
Octal D-type flip-flop with data enable; positive-edge trigger 文件：721.41 Kbytes Page：18 Pages | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger 文件：721.41 Kbytes Page：18 Pages | NEXPERIA 安世 | | ||
Octal D-type flip-flop with data enable; positive-edge trigger 文件：721.41 Kbytes Page：18 Pages | NEXPERIA 安世 | |
74HCT377产品属性
- 类型
描述
- VCC (V)：
4.5 - 5.5
- Logic switching levels：
TTL
- Output drive capability (mA)：
± 6
- tpd (ns)：
14
- fmax (MHz)：
53
- Power dissipation considerations：
low
- Tamb (°C)：
-40~125
- Rth(j-a) (K/W)：
80
- Ψth(j-top) (K/W)：
22.7
- Rth(j-c) (K/W)：
56
- Package name：
SO20
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
Nexperia USA Inc. |
24+25+ |
16500 |
全新原厂原装现货!受权代理!可送样可提供技术支持! |
||||
TI |
25+ |
6 |
公司优势库存 热卖中!! |
||||
Nexperia USA Inc. |
23+ |
20-SO |
3600 |
只做原装,假一赔十 |
|||
PHI |
00+/01+ |
NULL |
2109 |
全新原装100真实现货供应 |
|||
PHI |
25+23+ |
28554 |
绝对原装正品全新进口深圳现货 |
||||
PHI |
2402+ |
TSSOP-20 |
8324 |
原装正品!实单价优! |
|||
PHI |
25+ |
7.2mm |
2987 |
只售原装自家现货!诚信经营!欢迎来电! |
|||
NEXPERIA/安世 |
2022+ |
38 |
6600 |
只做原装,假一罚十,长期供货。 |
|||
Nexperia |
26+ |
Modules |
100000 |
现货~进口原装|遥遥领先 |
|||
PHI |
0047+ |
TSSOP |
1351 |
全新 发货1-2天 |
74HCT377规格书下载地址
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DdatasheetPDF页码索引
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