3-8 decoder/demultiplexer; inverter

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3-to-8 line decoder/demultiplexer; inverting

The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy par • Complies with JEDEC standard no. 7A\n• Input levels:• For 74HC138: CMOS level\n• For 74HCT138: TTL level\n\n• Demultiplexing capability\n• Multiple input enable for easy expansion\n• Ideal for memory chip select decoding\n• Active LOW mutually exclusive outputs\n• ESD protection:• HBM JESD22-A114F;

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple ena

3-to-8 line decoder/demultiplexer; inverting

3-to-8 line decoder/demultiplexer inverting

3-to-8 line decoder/demultiplexer; inverting

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74HC138-Q100; 74HCT138-Q100 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This m

3-to-8 line decoder/demultiplexer; inverting

The 74HC138-Q100; 74HCT138-Q100 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allow • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Complies with JEDEC standard no. 7A\n• Input levels:• For 74HC138-Q100: CMOS level\n• For 74HCT138-Q100: TTL level\n\n• Demultiplexing capability\n• Multiple inpu;

3-to-8 line decoder/demultiplexer; inverting

封装/外壳：16-VFQFN 裸露焊盘 包装：管件 描述：IC DECODER/DEMUX 1X3:8 16DHVQFN 集成电路（IC） 信号开关，多路复用器，解码器

封装/外壳：16-VFQFN 裸露焊盘 包装：卷带（TR） 描述：IC DECODER/DEMUX 1X3:8 16DHVQFN 集成电路（IC） 信号开关，多路复用器，解码器

3-to-8 line decoder/demultiplexer; inverting

GENERAL DESCRIPTION The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for memory

1-of-8 Decoder/Demultiplexer

The MC74HC138A is identical in pinout to the LS138. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC138A decodes a three−bit Address to one−of−eight active−low outputs. This device features three Chip Select inputs,

1-of-8 Decoder/Demultiplexer

The MC74HC138A is identical in pinout to the LS138. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC138A decodes a three−bit Address to one−of−eight active−low outputs. This device features three Chip Select inputs,

1-of-8 Decoder/Demultiplexer

The MC74HC138A is identical in pinout to the LS138. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC138A decodes a three−bit Address to one−of−eight active−low outputs. This device features three Chip Select inputs,

1-of-8 Decoder/Demultiplexer

The MC74HC138A is identical in pinout to the LS138. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC138A decodes a three−bit Address to one−of−eight active−low outputs. This device features three Chip Select inputs,