Quad 3?뭆tate Noninverting Buffers

The 74HC125 is identical in pinout to the LS125. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125 noninverting buffer is designed to be used with 3−state memory address drivers, clock drivers, and other bus−orien

Quad 3?뭆tate Noninverting Buffers

Quad 3−State Noninverting Buffers High−Performance Silicon−Gate CMOS The MC74HC125A and MC74HC126A are identical in pinout to the LS125 and LS126. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125A and HC126A n

Quad buffer/line driver; 3-state

GENERAL DESCRIPTION The 74HC/HCT125 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: bus driver • ICC category: MSI

QUADRUPLE 3-STATE BUFFERS OE LOW

Description The 74HC125 provides provides four independent buffer gates with 3-state outputs. Each buffer has a separate enable pin that if driven with a high logic level places the corresponding output in the high impedance state. The device is designed for operation with a power supply range of

Quad buffer/line driver; 3-state

1. General description The 74HC125; 74HCT125 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to

QUADRUPLE 3-STATE BUFFERS OE LOW

Description The 74HC125 provides provides four independent buffer gates with 3-state outputs. Each buffer has a separate enable pin that if driven with a high logic level places the corresponding output in the high impedance state. The device is designed for operation with a power supply range of

QUADRUPLE 3-STATE BUFFERS OE LOW

Description The 74HC125 provides provides four independent buffer gates with 3-state outputs. Each buffer has a separate enable pin that if driven with a high logic level places the corresponding output in the high impedance state. The device is designed for operation with a power supply range of

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC BUFFER NON-INVERT 6V 14SO 集成电路（IC） 缓冲器，驱动器，接收器，收发器