4-2-3-2-input AND-OR-invert gate

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4-2-3-2-Input AND-OR-Invert Gate

General Description This device contains gates configured to perform a 4-2-3-2 input AND-OR-INVERT function.

4-2-3-2-Input AND-OR-Invert Gate

文件：130.35 Kbytes Page：6 Pages

4-2-3-2-input AND-OR-invert gate

4-2-3-2-Input AND-OR-Invert Gate

4-2-3-2-Input AND-OR-Invert Gate

Octal bus transceiver, inverting 3-State

DESCRIPTION The 74F640 is an octal transceiver featuring inverting 3-State bus compatible outputs in both transmit and receive directions. The B port outputs are capable of sinking 64mA and sourcing 15mA, providing very good capacitive drive characteristics. The device features an Output Enable

Octal Bus Transceiver with 3-STATE Outputs

General Description These devices are octal bus transceivers designed for asynchronous two-way data flow between the A and B busses. Both busses are capable of sinking 64 mA, have 3- STATE outputs, and a common output enable pin. The direction of data flow is determined by the transmit/receive (T

Octal Bus Transceiver with 3-STATE Outputs

General Description These devices are octal bus transceivers designed for asynchronous two-way data flow between the A and B busses. Both busses are capable of sinking 64 mA, have 3- STATE outputs, and a common output enable pin. The direction of data flow is determined by the transmit/receive (T

Octal Bus Transceiver with 3-STATE Outputs

General Description These devices are octal bus transceivers designed for asynchronous two-way data flow between the A and B busses. Both busses are capable of sinking 64 mA, have 3- STATE outputs, and a common output enable pin. The direction of data flow is determined by the transmit/receive (T

Transceivers

74F641 Octal Bus Transceiver with Common Output Enable, Non-Inverting (Open Collector) 74F642 Octal Bus Transceiver with Common Output Enable, Inverting (Open Collector) FEATURES • High-impedance NPN base inputs for reduced loading (20µA in High and Low states) • Octal bidirectional bus in

Transceivers

74F641 Octal Bus Transceiver with Common Output Enable, Non-Inverting (Open Collector) 74F642 Octal Bus Transceiver with Common Output Enable, Inverting (Open Collector) FEATURES • High-impedance NPN base inputs for reduced loading (20µA in High and Low states) • Octal bidirectional bus in

Octal Bus Transceiver with 3-STATE Outputs

General Description These devices are octal bus transceivers designed for asynchronous two-way data flow between the A and B busses. Both busses are capable of sinking 64 mA, have 3- STATE outputs, and a common output enable pin. The direction of data flow is determined by the transmit/receive (T

Octal Bus Transceiver with 3-STATE Outputs

General Description These devices are octal bus transceivers designed for asynchronous two-way data flow between the A and B busses. Both busses are capable of sinking 64 mA, have 3- STATE outputs, and a common output enable pin. The direction of data flow is determined by the transmit/receive (T

Octal Transceiver/Register with 3-STATE Outputs

General Description These devices consist of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the a

Octal transceiver/register, non-inverting 3-State

DESCRIPTION The 74F646/74F646A and 74F648/74F648A transceivers/registers consist of bus transceiver circuits with 3–state outputs, D–type flip–flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus

Octal transceiver/register, non-inverting 3-State

DESCRIPTION The 74F646/74F646A and 74F648/74F648A transceivers/registers consist of bus transceiver circuits with 3–state outputs, D–type flip–flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus

Octal Transceiver/Register with 3-STATE Outputs

General Description These devices consist of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the a

Octal Transceiver/Register with 3-STATE Outputs

General Description These devices consist of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the a

Octal Transceiver/Register with 3-STATE Outputs

General Description These devices consist of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the a

Octal Transceiver/Register with 3-STATE Outputs

General Description These devices consist of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the a

Octal Transceiver/Register with 3-STATE Outputs

General Description These devices consist of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the a

Octal transceiver/register, non-inverting open-collector

DESCRIPTION The 74F647 and 74F649 Transceivers/Registers consist of bus transceiver circuits with open-collector outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will

Octal transceiver/register, non-inverting 3-State

DESCRIPTION The 74F646/74F646A and 74F648/74F648A transceivers/registers consist of bus transceiver circuits with 3–state outputs, D–type flip–flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus

Octal transceiver/register, non-inverting 3-State

DESCRIPTION The 74F646/74F646A and 74F648/74F648A transceivers/registers consist of bus transceiver circuits with 3–state outputs, D–type flip–flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus

Octal Transceiver/Register with 3-STATE Outputs

General Description These devices consist of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the a

Octal Transceiver/Register with 3-STATE Outputs

General Description These devices consist of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the a

Octal transceiver/register, non-inverting open-collector

DESCRIPTION The 74F647 and 74F649 Transceivers/Registers consist of bus transceiver circuits with open-collector outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will

4-2-3-2-Input AND-OR-Invert Gate

General Description This device contains gates configured to perform a 4-2-3-2 input AND-OR-INVERT function.

4-2-3-2-Input AND-OR-Invert Gate

General Description This device contains gates configured to perform a 4-2-3-2 input AND-OR-INVERT function.

4-2-3-2-Input AND-OR-Invert Gate

General Description This device contains gates configured to perform a 4-2-3-2 input AND-OR-INVERT function.

Octal Transceiver/Register with 3-STATE Outputs

文件：71.76 Kbytes Page：6 Pages

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

Octal Transceiver/Register with 3-STATE Outputs

文件：71.76 Kbytes Page：6 Pages

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

封装/外壳：24-SOIC（0.295"，7.50mm 宽） 包装：管件 描述：IC TXRX NON-INVERT 5.5V 24SOP 集成电路（IC） 缓冲器，驱动器，接收器，收发器

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

封装/外壳：24-DIP（0.300"，7.62mm） 包装：管件 描述：IC TXRX NON-INVERT 5.5V 24DIP 集成电路（IC） 缓冲器，驱动器，接收器，收发器

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes Page：12 Pages