20-bit registered driver with inverted register enable and Dynamic Controlled Outputs (3-State)

DESCRIPTION The 74AVC16836A is a 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance stat

20-bit registered driver with inverted register enable and Dynamic Controlled Outputs; 3-state

1. General description The 74AVC16836A is a 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-i

20-bit registered driver with inverted register enable and Dynamic Controlled OutputsE (3-State)

文件：127.19 Kbytes Page：11 Pages

20-bit registered driver with inverted register enable and Dynamic Controlled Outputs (3-State)

DESCRIPTION The 74AVC16836A is a 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance stat

20-bit registered driver with inverted register enable and Dynamic Controlled Outputs; 3-state

1. General description The 74AVC16836A is a 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-i

20-bit registered driver with inverted register enable and Dynamic Controlled Outputs; 3-state

The 74AVC16836A is a 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP).\n This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption.\n To ensure the high-impedance state durin • Wide supply voltage range from 1.2 V to 3.6 V\n• Complies with JEDEC standards:• JESD8-7 (1.2 V to 1.95 V)\n• JESD8-5 (1.8 V to 2.7 V)\n• JESD8-1A (2.7 V to 3.6 V)\n\n• CMOS low power consumption\n• Input/output tolerant up to 3.6 V\n• Dynamic Controlled Output (DCO) circuit dynamically changes ou;

20-bit registered driver with inverted register enable and Dynamic Controlled Outputs (3-State)

DESCRIPTION The 74AVC16836A is a 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance stat

20-bit registered driver with inverted register enable and Dynamic Controlled OutputsE (3-State)

文件：127.19 Kbytes Page：11 Pages

封装/外壳：56-TFSOP（0.240"，6.10mm 宽） 包装：管件 描述：IC BUF NON-INVERT 3.6V 56TSSOP 集成电路（IC） 缓冲器，驱动器，接收器，收发器

封装/外壳：56-TFSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC BUF NON-INVERT 3.6V 56TSSOP 集成电路（IC） 缓冲器，驱动器，接收器，收发器

20-bit registered driver with inverted register enable 3-State

DESCRIPTION The 74AVC16836 is a 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance state

20-bit registered driver with inverted register enable 3-State

DESCRIPTION The 74AVC16836 is a 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance state

2.5V 20-Bit Universal Bus Driver with 3-State Outputs

Product Description PI74AVC+16244 is a non-inverting 16-bit buffer/driver designed for low-voltage 1.65V to 3.6V VCC operation. The buffer/driver is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and