Low-power buffer with voltage-level translator

1. General description The 74AUP1T17 provides the single buffer function. This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. The 74AUP1T17 is designed for logic-level translation applications with input switching levels that acc

Low-power buffer with voltage-level translator

1. General description The 74AUP1T17 provides the single buffer function. This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. The 74AUP1T17 is designed for logic-level translation applications with input switching levels that acc

封装/外壳：4-XFDFN 裸露焊盘 包装：卷带（TR）卷带（TR） 描述：IC BUF NON-INVERT 3.6V 5X2SON 集成电路（IC） 缓冲器，驱动器，接收器，收发器

Low-power buffer with voltage-level translator

1. General description The 74AUP1T17 provides the single buffer function. This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. The 74AUP1T17 is designed for logic-level translation applications with input switching levels that acc

SN74AUP1T17 Low Power, 1.8/2.5/3.3-V Input, 3.3-V CMOS Output, Single Schmitt-Trigger Buffer Gate

1 Features 1• Single-Supply Voltage Translator • Output Level Up to Supply V CC CMOS Level – 1.8 V to 3.3 V (at VCC = 3.3 V) – 2.5 V to 3.3 V (at VCC = 3.3 V) – 1.8 V to 2.5 V (at VCC = 2.5 V) – 3.3 V to 2.5 V (at VCC = 2.5 V • Schmitt-Trigger Inputs Reject Input Noise and Provide Better O

LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE SCHMITT-TRIGGER BUFFER GATE

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