Low-power buffer with voltage-level translator

Features « Wide supply voltage range from 23V 1036 | « Inputs accept voltages up to 3.6V o lore supports partial-power-down mode o Low static power consumption; lcc=1.5pA (Max.) » ESD Protection Exceeds JESD 22 -2000-V Human-Body Model (A114-A) -200-V Machine Model (A115-A) | ~1000-V Charg

Low-power buffer with voltage-level translator

1. General description The 74AUP1T17 provides the single buffer function. This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. The 74AUP1T17 is designed for logic-level translation applications with input switching levels that acc

Low-power buffer with voltage-level translator

1. General description The 74AUP1T17 provides the single buffer function. This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. The 74AUP1T17 is designed for logic-level translation applications with input switching levels that acc

Low-power buffer with voltage-level translator

1. General description The 74AUP1T17 provides the single buffer function. This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. The 74AUP1T17 is designed for logic-level translation applications with input switching levels that acc

LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE SCHMITT-TRIGGER BUFFER GATE

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