型号 功能描述 生产厂家 企业 LOGO 操作
74ALVC16835MTD

Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs

General Description The ALVC16835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes.The 74ALVC16835 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V. The 74A

Fairchild

仙童半导体

Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs

General Description The ALVC16835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes.The 74ALVC16835 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V. The 74A

Fairchild

仙童半导体

18-bit registered driver; 3-state

1 General description The 74ALVC16835A is a 18–bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is la

NEXPERIA

安世

18-bit registered driver 3-State

DESCRIPTION The 74ALVC16835A is a 18–bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on

Philips

飞利浦

18-bit registered driver 3-State

DESCRIPTION The 74ALVC16835A is a 18–bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on

Philips

飞利浦

18-bit registered driver; 3-state

1 General description The 74ALVC16835A is a 18–bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is la

NEXPERIA

安世

74ALVC16835MTD产品属性

  • 类型

    描述

  • 型号

    74ALVC16835MTD

  • 功能描述

    总线收发器 18-Bit Universal Bus

  • RoHS

  • 制造商

    Fairchild Semiconductor

  • 逻辑类型

    CMOS

  • 逻辑系列

    74VCX

  • 每芯片的通道数量

    16

  • 输入电平

    CMOS

  • 输出电平

    CMOS

  • 输出类型

    3-State

  • 高电平输出电流

    - 24 mA

  • 低电平输出电流

    24 mA

  • 传播延迟时间

    6.2 ns

  • 电源电压-最大

    2.7 V, 3.6 V

  • 电源电压-最小

    1.65 V, 2.3 V

  • 最大工作温度

    + 85 C

  • 封装/箱体

    TSSOP-48

  • 封装

    Reel

更新时间:2025-11-19 17:48:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
RENESAS(瑞萨)/IDT
24+
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7350
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恩XP
24+
SO-14
30000
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25+
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2700
全新原装自家现货优势!
恩XP
21+
SO-14
8080
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Nexperia USA Inc.
24+
56-TSSOP
65200
一级代理/放心采购
恩XP
23+
SO-14
8080
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原厂
25+
45
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PHI
00+
TSOP56
32
全新原装100真实现货供应
24+
5000
公司存货
恩XP
25+
SOT364
188600
全新原厂原装正品现货 欢迎咨询

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