18-bit registered driver 3-State

DESCRIPTION The 74ALVC16835A is a 18–bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on

18-bit registered driver; 3-state

1 General description The 74ALVC16835A is a 18–bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is la

Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs

General Description The ALVC16835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes.The 74ALVC16835 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V. The 74A

18-bit registered driver; 3-state

1 General description The 74ALVC16835A is a 18–bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is la

18-bit registered driver 3-State

DESCRIPTION The 74ALVC16835A is a 18–bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on

74ALVC16835A_15

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封装/外壳：56-TFSOP（0.240"，6.10mm 宽） 包装：管件 描述：IC BUF NON-INVERT 3.6V 56TSSOP 集成电路（IC） 缓冲器，驱动器，接收器，收发器

封装/外壳：56-TFSOP（0.240"，6.10mm 宽） 包装：管件 描述：IC BUF NON-INVERT 3.6V 56TSSOP 集成电路（IC） 缓冲器，驱动器，接收器，收发器