74ACT109价格
参考价格：￥2.6945
型号：74ACT109PC 品牌：Fairchild 备注：这里有74ACT109多少钱，2026年最近7天走势，今日出价，今日竞价，74ACT109批发/采购报价，74ACT109行情走势销售排行榜，74ACT109报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
74ACT109 | Dual JK Positive Edge-Triggered Flip-Flop General Description The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecti | FAIRCHILD 仙童半导体 |   | |
74ACT109 | Dual JK Positive Edge?뭈riggered Flip?묯lop The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J | ONSEMI 安森美半导体 | | |
74ACT109 | Dual JK Positive Edge-Triggered Flip-Flop 文件：339.62 Kbytes Page：12 Pages | FAIRCHILD 仙童半导体 | | |
Dual JK Positive Edge-Triggered Flip-Flop General Description The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecti | FAIRCHILD 仙童半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop Features ■ ICC reduced by 50% ■ Outputs source/sink 24mA ■ ACT109 has TTL-compatible inputs General Description The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock wav | ONSEMI 安森美半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop Features ■ ICC reduced by 50% ■ Outputs source/sink 24mA ■ ACT109 has TTL-compatible inputs General Description The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock wav | ONSEMI 安森美半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop General Description The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecti | FAIRCHILD 仙童半导体 | | ||
封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF JK TYPE DUAL 1BIT 16TSSOP 集成电路（IC） 触发器 | ONSEMI 安森美半导体 | | ||
IC FF JK TYPE DUAL 1BIT 16TSSOP | ONSEMI 安森美半导体 | | ||
封装/外壳：16-DIP（0.300"，7.62mm） 功能：设置（预设）和复位 包装：管件 描述：IC FF JK TYPE DUAL 1BIT 16DIP 集成电路（IC） 触发器 | ONSEMI 安森美半导体 | | ||
IC FF JK TYPE DUAL 1BIT 16DIP | ONSEMI 安森美半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop 文件：339.62 Kbytes Page：12 Pages | FAIRCHILD 仙童半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop 文件：339.62 Kbytes Page：12 Pages | FAIRCHILD 仙童半导体 | | ||
IC FF JK TYPE DUAL 1BIT 16SOIC | ONSEMI 安森美半导体 | | ||
Dual JK Positive Edge?뭈riggered Flip?묯lop The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J | ONSEMI 安森美半导体 | | ||
Dual JK Positive Edge?뭈riggered Flip?묯lop The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J | ONSEMI 安森美半导体 | | ||
Dual JK Positive Edge?뭈riggered Flip?묯lop The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J | ONSEMI 安森美半导体 | | ||
Dual JK Positive Edge?뭈riggered Flip?묯lop The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J | ONSEMI 安森美半导体 | |
74ACT109产品属性
- 类型
描述
- 类型：
JK 型
- 输出类型：
差分
- 元件数：
2
- 每元件位数：
1
- 时钟频率：
210MHz
- 不同 V，最大 CL 时的最大传播延迟：
11ns @ 5V，50pF
- 触发器类型：
正边沿
- 电流 - 输出高，低：
24mA，24mA
- 电压 - 电源：
4.5 V ~ 5.5 V
- 电流 - 静态（Iq)：
20µA
- 输入电容：
4.5pF
- 工作温度：
-40°C ~ 85°C（TA）
- 安装类型：
表面贴装
- 封装/外壳：
16-TSSOP（0.173\，4.40mm 宽）
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
NS |
24+ |
DIP |
5000 |
全新原装正品,现货销售 |
|||
onsemi(安森美) |
25+ |
SOP16 |
3238 |
原装现货,免费供样,技术支持,原厂对接 |
|||
FAIRCHILD/仙童 |
23+ |
SOP16 |
5000 |
原厂授权代理,海外优势订货渠道。可提供大量库存,详 |
|||
26+ |
N/A |
72000 |
一级代理-主营优势-实惠价格-不悔选择 |
||||
NATIONAL |
25+ |
NA |
880000 |
明嘉莱只做原装正品现货 |
|||
FAIR |
最新 |
SOP |
10000 |
公司进口原装特价处理 |
|||
Fairchild Semiconductor |
24+25+ |
16500 |
全新原厂原装现货!受权代理!可送样可提供技术支持! |
||||
FAIRCHILD/仙童 |
23+ |
SOP-16 |
50000 |
全新原装正品现货,支持订货 |
|||
ON/安森美 |
25+ |
电联咨询 |
7800 |
公司现货,提供拆样技术支持 |
|||
Fairchild(飞兆/仙童) |
23+ |
NA |
20094 |
正纳10年以上分销经验原装进口正品做服务做口碑有支持 |
74ACT109规格书下载地址
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DdatasheetPDF页码索引
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