HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER

FEATURES: • A and C grades • Low input and output leakage ≤1μA (max.) • CMOS power levels • True TTL input and output compatibility: – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) • High Drive outputs (-15mA IOH, 48mA IOL) • Meets or exceeds JEDEC standard 18 specifications • Power off disable o

HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER

FEATURES: • A and C grades • Low input and output leakage ≤1μA (max.) • CMOS power levels • True TTL input and output compatibility: – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) • High Drive outputs (-15mA IOH, 48mA IOL) • Meets or exceeds JEDEC standard 18 specifications • Power off disable o

HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER

FEATURES: • A and C grades • Low input and output leakage ≤1μA (max.) • CMOS power levels • True TTL input and output compatibility: – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) • High Drive outputs (-15mA IOH, 48mA IOL) • Meets or exceeds JEDEC standard 18 specifications • Power off disable o

HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER

FEATURES: • A and C grades • Low input and output leakage ≤1μA (max.) • CMOS power levels • True TTL input and output compatibility: – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) • High Drive outputs (-15mA IOH, 48mA IOL) • Meets or exceeds JEDEC standard 18 specifications • Power off disable o

HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER

FEATURES: • A and C grades • Low input and output leakage ≤1μA (max.) • CMOS power levels • True TTL input and output compatibility: – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) • High Drive outputs (-15mA IOH, 48mA IOL) • Meets or exceeds JEDEC standard 18 specifications • Power off disable o

HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER

FEATURES: • A and C grades • Low input and output leakage ≤1μA (max.) • CMOS power levels • True TTL input and output compatibility: – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) • High Drive outputs (-15mA IOH, 48mA IOL) • Meets or exceeds JEDEC standard 18 specifications • Power off disable o

HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER

FEATURES: • A and C grades • Low input and output leakage ≤1μA (max.) • CMOS power levels • True TTL input and output compatibility: – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) • High Drive outputs (-15mA IOH, 48mA IOL) • Meets or exceeds JEDEC standard 18 specifications • Power off disable o

HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER

FEATURES: • A and C grades • Low input and output leakage ≤1μA (max.) • CMOS power levels • True TTL input and output compatibility: – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) • High Drive outputs (-15mA IOH, 48mA IOL) • Meets or exceeds JEDEC standard 18 specifications • Power off disable o

Aluminum Electrolytic Capacitors Power Long Life 4-Terminal Snap-In

文件：136.45 Kbytes Page：7 Pages

包装：盒 描述：KIT DESIGN FOR WLAN 套件 其它

包装：袋 描述：CONN D-SUB FEMALE SCREW LOCK 连接器，互连器件 D-Sub，D 形连接器顶丝

连接器附件

3 MSPS, 12-Bit SAR ADC

GENERAL DESCRIPTION The AD7482 is a 12-bit, high speed, low power, successive approximation ADC. The part features a parallel interface with throughput rates up to 3 MSPS. The part contains a low noise, wide bandwidth track-and-hold that can handle input frequencies in excess of 40 MHz. FEATURES

3MSPS, 12-Bit SAR ADC

GENERAL DESCRIPTION The AD7482 is a 12-bit, high speed, low power, successive approximation ADC. The part features a parallel interface with throughput rates up to 3 MSPS. The part contains a low noise, wide bandwidth track-and-hold that can handle input frequencies in excess of 40 MHz. FEATURES

3MSPS, 12-Bit SAR ADC

GENERAL DESCRIPTION The AD7482 is a 12-bit, high speed, low power, successive approximation ADC. The part features a parallel interface with throughput rates up to 3 MSPS. The part contains a low noise, wide bandwidth track-and-hold that can handle input frequencies in excess of 40 MHz. FEATURES

3 MSPS, 12-Bit SAR ADC

文件：566.63 Kbytes Page：21 Pages

3 MSPS, 12-Bit SAR ADC

文件：566.63 Kbytes Page：21 Pages

Transistor transistor logic