64K x 32 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect

Features ◆ 64K x 32 memory configuration ◆ Supports high system speed: Commercial and Industrial: – 5 5ns clock access time (100 MHz) – 6 6ns clock access time (83 MHz) – 7 7ns clock access time (66 MHz) ◆ Single-cycle deselect functionality ◆ LBO input selects interleaved or linear burst

封装/外壳：100-LQFP 包装：卷带（TR） 描述：IC SRAM 2MBIT PARALLEL 100TQFP 集成电路（IC） 存储器

64K x 32 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect

Features ◆ 64K x 32 memory configuration ◆ Supports high system speed: Commercial and Industrial: – 5 5ns clock access time (100 MHz) – 6 6ns clock access time (83 MHz) – 7 7ns clock access time (66 MHz) ◆ Single-cycle deselect functionality ◆ LBO input selects interleaved or linear burst

封装/外壳：100-LQFP 包装：卷带（TR） 描述：IC SRAM 2MBIT PARALLEL 100TQFP 集成电路（IC） 存储器

64K x 32 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect

Features ◆ 64K x 32 memory configuration ◆ Supports high system speed: Commercial and Industrial: – 5 5ns clock access time (100 MHz) – 6 6ns clock access time (83 MHz) – 7 7ns clock access time (66 MHz) ◆ Single-cycle deselect functionality ◆ LBO input selects interleaved or linear burst

64K x 32 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect

Features ◆ 64K x 32 memory configuration ◆ Supports high system speed: Commercial and Industrial: – 5 5ns clock access time (100 MHz) – 6 6ns clock access time (83 MHz) – 7 7ns clock access time (66 MHz) ◆ Single-cycle deselect functionality ◆ LBO input selects interleaved or linear burst

3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect

文件：861.88 Kbytes Page：18 Pages

64K x 32 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect

文件：273.18 Kbytes Page：19 Pages