封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC PLL BUILDING BLOCK 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC PLL BUILDING BLOCK 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

PLL Building Block

Description The ICS673-01 is a low cost, high performance Phase Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO), and two output buffers. One output buffer is a divide by two of

PLL Building Block

Description The ICS673-01 is a low cost, high performance Phase Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO), and two output buffers. One output buffer is a divide by two of

PLL Building Block

Description The ICS673-01 is a low cost, high performance Phase Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO), and two output buffers. One output buffer is a divide by two of

PLL Building Block

Description The ICS673-01 is a low cost, high performance Phase Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO), and two output buffers. One output buffer is a divide by two of