Quadraclock Quadrature Delay Buffer

The 672-01/02 are zero delay buffers that generate four output clocks whose phases are spaced at 90° intervals. Based on IDT's proprietary low jitter Phase-Locked Loop (PLL) techniques, each device provides five low-skew outputs, with clock rates up to 84 MHz for the 672-01 and up to 135 MHz for the • Packaged in 16-pin SOIC\n• Input clock range from 5 MHz to 150 MHz (depends multiplier)\n• Zero input-output delay\n• Four accurate (<250 ps) outputs with 0°, 90°, 180°, and 270° phase shift from ICLK, and one FBCLK (0°)\n• Full CMOS outputs (TTL compatible)\n• Includes Power-down for power saving;