LOW SKEW CLOCK INVERTER AND DIVIDER

Features • Packaged in 16-pin SOIC (150 mil) • Input clock up to 160 MHz in the non-PLL mode • Provides clock outputs of CLK, CLK, and CLK/2 • Low skew (500 ps) on CLK, CLK, and CLK/2 • All outputs can be tri-stated • Entire chip can be powered down by changing one or two select pins • 3.3

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC CLK INVERTER/DIVIDER 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

LOW SKEW CLOCK INVERTER AND DIVIDER

Features • Packaged in 16-pin SOIC (150 mil) • Input clock up to 160 MHz in the non-PLL mode • Provides clock outputs of CLK, CLK, and CLK/2 • Low skew (500 ps) on CLK, CLK, and CLK/2 • All outputs can be tri-stated • Entire chip can be powered down by changing one or two select pins • 3.3

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC CLK INVERTER/DIVIDER 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

LOW SKEW CLOCK INVERTER AND DIVIDER

Description The ICS548A-03 is a low cost, low skew, high-performance general purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-two. Using our patented Phase-Locked Loop (PLL) techniques, the device operates from a frequency range of 1

LOW SKEW CLOCK INVERTER AND DIVIDER

Description The ICS548A-03 is a low cost, low skew, high-performance general purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-two. Using our patented Phase-Locked Loop (PLL) techniques, the device operates from a frequency range of 1