CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB

Features • Packaged as 28-pin SSOP (150 mil body) • Synchronizes fractional clocks rising edges • CMOS in to PECL out • PECL in to PECL out • Pin selectable dividers • Zero input to output skew • User determines the output frequency - no software needed • Slices frequency or period • Inp

封装/外壳：28-SSOP（0.154"，3.90mm 宽） 包装：管件 描述：IC CLK SLICER PECL ZDB 28-SSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB

Features • Packaged as 28-pin SSOP (150 mil body) • Synchronizes fractional clocks rising edges • CMOS in to PECL out • PECL in to PECL out • Pin selectable dividers • Zero input to output skew • User determines the output frequency - no software needed • Slices frequency or period • Inp

Clock Slicer User Configurable PECL input Zero Delay Buffer

Description The ICS527-04 Clock Slicer is the most flexible way to generate an output clock from an input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplicat

Clock Slicer User Configurable PECL input Zero Delay Buffer

Description The ICS527-04 Clock Slicer is the most flexible way to generate an output clock from an input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplicat