3.3V ZERO DELAY CLOCK BUFFER

FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five outputs • Zero Input-Output Delay • Output Skew

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC CLK BUFFER ZD 3.3V 8-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3V ZERO DELAY CLOCK BUFFER

FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five outputs • Zero Input-Output Delay • Output Skew

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC CLK BUFFER ZD 3.3V 8-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3V ZERO DELAY CLOCK BUFFER

FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five outputs • Zero Input-Output Delay • Output Skew

3.3V ZERO DELAY CLOCK BUFFER

FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five outputs • Zero Input-Output Delay • Output Skew

3.3V ZERO DELAY CLOCK BUFFER

FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five outputs • Zero Input-Output Delay • Output Skew

3.3V ZERO DELAY CLOCK BUFFER

DESCRIPTION: The IDT2305A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. FEATURE