PDH System Synchronizer

The ZL30102 is a high-performance DPLL (digital phase-locked loop) designed for synchronization and timing control of redundant system clocks requiring Stratum 4/4E timing specifications. The ZL30102 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of three netwo Accepts three input references and synchronizes to any combination of 8 kHz, 1.544, 2.048, 8.192 or 16.384 MHz inputs\nSynchronizes to clock-and-sync-pair to maintain minimal phase skew between redundant primary and a secondary clocks\nProvides a range of clock outputs: 1.544, 2.048, 3.088, 6.312 an;

T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110

文件：481.47 Kbytes Page：50 Pages

T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110

文件：988.22 Kbytes Page：48 Pages

T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110

文件：481.47 Kbytes Page：50 Pages

T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110

文件：988.22 Kbytes Page：48 Pages

封装/外壳：64-TQFP 包装：卷带（TR） 描述：IC PHASE LOCK LOOP DGTL 64TQFP 集成电路（IC） 应用特定时钟/定时

T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110

文件：988.22 Kbytes Page：48 Pages

3.0x1.0mm RIGHT ANGLE SMD CHIP LED LAMPS

文件：578.39 Kbytes Page：6 Pages

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

文件：3.30221 Mbytes Page：164 Pages

64/32-bit Microprocessor

文件：2.89072 Mbytes Page：701 Pages