3.3V LVT 16-bit edge-triggered D-type flip-flop 3-State

DESCRIPTION The 74LVT16374A is a high-performance BiCMOS product designed for VCC operation at 3.3V. This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-State outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition

2.5V/3.3V 16-bit edge-triggered D-type flip-flop 3-State

DESCRIPTION The 74ALVCH16374 is a 16-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-State outputs for bus oriented applications. Incorporates bus hold data inputs which eliminate the need for external pull-up or pull-down resistors to hold unused inputs. Th

2.5V/3.3V 16-bit edge-triggered D-type flip-flop 3-State

DESCRIPTION The 74ALVT16374 is a high-performance BiCMOS product designed for VCC operation at 2.5V or 3.3V with I/O compatibility up to 5V. This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-State outputs. The device can be used as two 8-bit flip-flops or one

16-bit D-type flip-flop; positive-edge trigger 3-State

DESCRIPTION The 74ABT16374B high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT16374B has two 8-bit, edge triggered registers, with each register coupled to eight 3-State output buffers. The two sections of each regist

16-bit D-type flip-flop; positive-edge trigger 3-State

DESCRIPTION The 74ABT16374B high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT16374B has two 8-bit, edge triggered registers, with each register coupled to eight 3-State output buffers. The two sections of each regist

16-bit D-type flip-flop; positive-edge trigger 3-State

DESCRIPTION The 74ABT16374B high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT16374B has two 8-bit, edge triggered registers, with each register coupled to eight 3-State output buffers. The two sections of each regist