NPN Mult i-Chip Built-in Resistors Transistor

Features * Mounting possible with UMT3 automatic mounting machines. * Transistor elements are independent, eliminating interference. * Mounting cost and area can be cut in half. * Two DTC114E chips in a UMT package

General purpose transistors (du al transistors)

FEATURES ● Two DTC114E chip in a package ● Mounting possible with SOT-363 automatic mounting machines ● Transistor elements are independent, eliminating interference ● Mounting cost and area be cut in half

Digital Transistors

Features • Two DTC114E Chip In a Package • Mounting Possible With SOT-363 Automatic Mounting Machines • Transistor Elements Independent, Eliminating Interference • Design For Saving Space and Cost • Halogen Free Available Upon Request By Adding Suffix -HF • Moisture Sensitivity Level 1 • Ep

General purpose (dual digital transistors)

Features 1) Two DTC114E chips in a EMT or UMT or SMT package. 2) Mounting possible with EMT3 or UMT3 or SMT3 automatic mounting machines. 3) Transistor elements are independent, eliminating interference. 4) Mounting cost and area can be cut in half.

General purpose (dual digital transistors)

Features 1) Two DTC114E chips in a EMT or UMT or SMT package. 2) Mounting possible with EMT3 or UMT3 or SMT3 automatic mounting machines. 3) Transistor elements are independent, eliminating interference. 4) Mounting cost and area can be cut in half.

DUAL Digital Transistor(NPNNPN)

Features ◇ Epitaxial planar die construction ◇ Surface device type mounting ◇ Moisture sensitivity level 1 ◇ Pb free version and RoHS compliant ◇ Two DTC114E chip in a package ◇ Mounting possible with SOT-363 automatic mounting machines ◇ Transistor elements are independent, eliminating int

Dual Digital Transistors

Dual Digital Transistors (NPN+NPN) FEATURES ● Two DTC114E chip in a package ● Mounting possible with SOT-363 automatic mounting machines ● Transistor elements are independent, eliminating interference ● Mounting cost and area be cut in half

DUAL Digital Transistor(NPNNPN)

Features ◇ Epitaxial planar die construction ◇ Surface device type mounting ◇ Moisture sensitivity level 1 ◇ Pb free version and RoHS compliant ◇ Two DTC114E chip in a package ◇ Mounting possible with SOT-363 automatic mounting machines ◇ Transistor elements are independent, eliminating int

NPN 100mA 50V Complex Digital Transistors (Bias Resistor Built-in Transistors)

Features 1) Two DTC114E chips in a EMT or UMT or SMT package. 2) Mounting possible with EMT3 or UMT3 or SMT3 automatic mounting machines. 3) Transistor elements are independent, eliminating interference. 4) Mounting cost and area can be cut in half.

小信号数字三极管

数字晶体管

双数字晶体管

General purpose (dual digital transistors)

文件：1.48724 Mbytes Page：9 Pages

General purpose (dual digital transistors)

文件：81.05 Kbytes Page：4 Pages

Digital Transistors

文件：213.47 Kbytes Page：3 Pages

NPN 100mA 50V Complex Digital Transistors (Bias Resistor Built-in Transistors)

Features 1) Two DTC114E chips in a EMT or UMT or SMT package. 2) Mounting possible with EMT3 or UMT3 or SMT3 automatic mounting machines. 3) Transistor elements are independent, eliminating interference. 4) Mounting cost and area can be cut in half.

Digital Transistors

文件：213.47 Kbytes Page：3 Pages

NPN Mult i-Chip

文件：477.2 Kbytes Page：2 Pages

General purpose (Dual digital transistors)

文件：1.07117 Mbytes Page：8 Pages