Functional Description

• 8-Bit Addressable Latch

General

The 74HC259D is a high speed CMOS ADDRESSABLE LATCH fabricated with silicon gate C2MOS technology.

It achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power

dissipation.

The respective bits are controlled by address inputs A, B, and C. When CLEAR input is held high and enable

input G is held low, the data is written into the bit selected by address inputs, the other bit hold their previous

conditions.

When both CLEAR and G held high, writing of all bits is inhibited regardless of adress inputs, and their previous

condition are held. When CLEAR is held low and G is held high, all bits are resent to low regardless of the other

inputs. When both of CLEAR and G held low, all bits which isn't selected by adress inputs are resent to low.

All inputs are equipped with protection circuits against static discharge or transient excess voltage.

Features

(1) High speed: tpd = 15 ns (typ.) at VCC = 5 V

(2) Low power dissipation: ICC = 4.0 μA (max) at Ta = 25 

(3) Balanced propagation delays: tPLH ≈ tPHL

(4) Wide operating voltage range: VCC(opr) = 2.0 to 6.0 V