1 Features

• AEC-Q100 qualified for automotive applications

• Core

– Arm® 32-bit Cortex® M0+ CPU with memory protection unit, frequency up to 80MHz

• Functional Safety-Compliant targeted

– Developed for functional safety applications

– Documentation to aid ISO 26262 system design will be available

– Systematic capability up to ASIL B planned

• PSA-L1 Certification planned

• Operating characteristics

– Extended temperature: –40°C up to 125°C

– Wide supply voltage range: 1.62V to 3.6V

• Memories

– Up to 256KB of flash memory with error correction code (ECC)

• Dual-bank with address swap for OTA updates

– 8KB data flash bank with ECC protection

– 32KB total SRAM with ECC protection or hardware parity

• High-performance analog peripherals

– Up to two simultaneous sampling 12-bit 1.6Msps analog-to-digital converters (ADC) with up to 27 external channels

• 14-bit effective resolution at 100ksps with hardware averaging

– Up to two high-speed comparators (COMP) with integrated 8-bit reference DACs

• 32ns propagation delay in high-speed mode

• Support low-power mode operation down to <1μA

– Programmable analog connections between ADC and COMP

– Two voltage references (VREF)

• Configurable 1.4V or 2.5V internal shared voltage reference with external VREF capacitor

• Configurable 1.4V or 2.5V internal only voltage reference without external VREF capacitor

– Integrated temperature sensor

• Optimized low-power modes (estimates for early samples)

– RUN: 104μA/MHz (CoreMark)

– SLEEP: 614uA at 4MHz

– STOP: 56μA at 32kHz

– STANDBY: 1.4μA at 32kHz with RTC and SRAM state retention

– SHUTDOWN: 69nA with IO wake-up capability