1 Features

• 2 V to 5.5 V VCC operation

• Maximum tpd of 14 ns at 5 V

• Supports mixed-mode voltage operation on all

ports

• Ioff supports partial-power-down mode operation

• Latch-up performance exceeds 250 mA

per JESD 17

• Operating ambient temperature: -55°C to +125°C

• Supports defense, aerospace, and medical

applications:

– Controlled baseline

– One assembly and test site

– One fabrication site

– Extended product life cycle

– Product traceability

2 Applications

• Synchronize inverted clock inputs

• Debounce a switch

• Invert a digital signal

3 Description

The SN74LV14B-EP device contains six independent

Inverter with Schmitt-trigger inputs designed for 2 V to

5.5 V VCC operation. Each gate performs the Boolean

function Y = A in positive logic.

This device is fully specified for partial-power-down

applications using Ioff. The Ioff circuitry disables

the outputs, preventing damaging current backflow

through the devices when they are powered down.