1.2 Features

The TSB12LV26-EP device supports the following features:

• Controlled Baseline

• One Assembly/Test Site, One Fabrication Site

• Extended Temperature Performance of −40°C to 110°C

• Enhanced Diminishing Manufacturing Sources (DMS) Support

• Enhanced Product Change Notification

• Qualification Pedigree†

• 3.3-V and 5-V PCI bus signaling

• 3.3-V supply (core voltage is internally regulated to 1.8 V)

• Serial bus data rates of 100M bits/s, 200M bits/s, and 400M bits/s

• Physical write posting of up to three outstanding transactions

• Serial ROM interface supports 2-wire devices

• External cycle timer control for customized synchronization

• PCI burst transfers and deep FIFOs to tolerate large host latency

• Two general-purpose I/Os

• Fabricated in advanced low-power CMOS process

• Packaged in 100-terminal LQFP (PZ)

• PCI_CLKRUN protocol