1 Features

• Qualified for automotive applications

– AEC-Q100 grade 1: –40 to 125°C TA

• Low EMI:

– Meets CISPR25 class 5 performance with no

additional components

• Integrated avalanche rated MOSFETs

– Designed and qualified for reliability for

dielectric withstand testing (Hi-Pot)

• TPSI2260-Q1: IAVA =1mA for 60s pulses

• TPSI2260T-Q1: IAVA = 3mA for 60s pulses

– 600V standoff voltage

– RON = 65Ω (TJ = 25°C)

– IOFF = 1.22μA at 500V (TJ = 105°C)

• Low primary side supply current

– 9mA ON state current

• Robust isolation barrier:

– > 38 year projected lifetime at 1000VRMS /

1500VDC working voltage

– Reinforced isolation rating, VISO, up to

5000VRMS

• SOIC 11-pin (DWQ) package with wide pins for

improved thermal performance

– Creepage and clearance ≥ 8mm (primarysecondary)

– Creepage and clearance ≥ 6mm (across switch

terminals)

• Safety-Related Certifications

– (Planned) DIN VDE V 0884-17:2021-10

– (Planned) UL 1577 component recognition

program

2 Applications

• Solid state relay

• Hybrid, electric, and power train systems

• Battery management systems (BMS)

• Solar energy

• Onboard charger

• EV charging infrastructure

• See also the TI Reference Designs related to

these applications.

3 Description

The TPSI2260-Q1 is an isolated solid state relay

designed for high voltage automotive and industrial

applications. The TPSI2260-Q1 uses TI's high

reliability reinforced capacitive isolation technology

in combination with internal back-to-back MOSFETs

to form a completely integrated solution requiring

no secondary side power supply. The TPSI2260-

Q1 improves system reliability as TI's capacitive

isolation technology does not suffer from mechanical

wearout or photo degradation failure modes common

in mechanical relay and photo relay components.

The primary side of the device is powered by only

9mA of input current and incorporates a fail-safe EN

pin preventing any possibility of back powering the

VDD supply. In most applications, the VDD pin of

the device should be connected to a system supply

between 4.5V–20V and the EN pin of the device

should be driven by a GPIO output with Logic low

between 2.1V–20V.

The secondary side consists of back-to-back

MOSFETs with a standoff voltage of ±600V from

S1 to S2. The TPSI2260-Q1 MOSFET avalanche

robustness and thermally conscious package design

allow it to robustly support system level dielectric

withstand testing (HiPot) and DC fast charger surge

currents of up to 1mA without requiring any external

components.