位置:TPS40200-Q1 > TPS40200-Q1详情

TPS40200-Q1中文资料

厂家型号

TPS40200-Q1

文件大小

995.86Kbytes

页面数量

50

功能描述

WIDE-INPUT-RANGE NONSYNCHRONOUS VOLTAGE-MODE CONTROLLER

数据手册

下载地址一下载地址二到原厂下载

生产厂商

TI2

TPS40200-Q1数据手册规格书PDF详情

1FEATURES

• Input Voltage Range 5.5 V to 52 V

• Output Voltage (700 mV to 87% VIN)

• 200-mA Internal P-Channel FET Driver

• Voltage Feed-Forward Compensation

• Undervoltage Lockout

• Programmable Fixed-Frequency

(35 kHz to 500 kHz) Operation

• Programmable Short-Circuit Protection

• Hiccup Overcurrent Fault Recovery

• Programmable Closed-Loop Soft Start

• 700-mV 1% Reference Voltage

• External Synchronization

APPLICATIONS

• Down-Hole Drilling

• High Temperature Environments

SUPPORTS EXTREME TEMPERATURE

APPLICATIONS

• Controlled Baseline

• One Assembly/Test Site

• One Fabrication Site

• Available in Extreme (–55°C/210°C)

Temperature Range (1)

• Extended Product Life Cycle

• Extended Product-Change Notification

• Product Traceability

• Texas Instruments high temperature products

utilize highly optimized silicon (die) solutions

with design and process enhancements to

maximize performance over extended

temperatures.

DESCRIPTION

The TPS40200 is a flexible nonsynchronous controller with a built-in 200-mA driver for P-channel FETs. The

circuit operates with inputs up to 52 V, with a power-saving feature that turns off driver current once the external

FET has been fully turned on. This feature extends the flexibility of the device, allowing it to operate with an input

voltage up to 52 V, without dissipating excessive power. The circuit operates with voltage-mode feedback and

has feed-forward input-voltage compensation that responds instantly to input-voltage change. The integral 700-

mV reference is trimmed to 2%, providing the means to accurately control low voltages. Clock frequency, soft

start, and overcurrent limit each are easily programmed by a single, external component. The part has

undervoltage lockout, and can be easily synchronized to other controllers or a system clock to satisfy sequencing

and/or noise-reduction requirements.

更新时间:2025-12-6 8:01:00
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