1FEATURES

23• 0.6- to 1.3-Gigabits Per Second (Gbps)

Serializer/Deserializer

• Low Power Consumption 250 mW (typ) at 1.25

Gbps

• LVPECL-Compatible Differential I/O on

High-Speed Interface

• Single Monolithic PLL Design

• Support For 10-Bit Interface

• Fast Relock Times Less Than 256 ns (typ)

Suitable for EPON/GEPON Applications such

as OLT and ONU Systems

• Receiver Differential-Input Thresholds, 200-mV

Minimum

• Industrial Temperature Range From –40°C to

85°C

• IEEE 802.3 Gigabit Ethernet Compliant

• Designed in 0.25 μm CMOS Technology

• No External Filter Capacitors Required

• Comprehensive Suite of Built-In Testability

• 2.5-V Supply Voltage for Lowest-Power

Operation

• 3.3-V Tolerant on LVTTL Inputs

• Hot Plug Protection

• 40-Pin 6-mm × 6-mm QFN PowerPAD™

Package

DESCRIPTION

The TLK1221 gigabit Ethernet transceiver provides for high-speed full-duplex point-to-point data transmissions.

These devices are based on the timing requirements of the 10-bit interface specification by the IEEE 802.3

Gigabit Ethernet specification. The TLK1221 supports data rates from 0.6 Gbps through 1.3 Gbps.

The primary application of these devices is to provide building blocks for point-to-point baseband data

transmission over controlled-impedance media of 50 Ω. The transmission media can be printed-circuit board

traces, copper cables or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon

the attenuation characteristics of the media and the noise coupling to the environment.

The TLK1221 performs the data serialization, deserialization, and clock extraction functions for a physical layer

interface device. The transceiver operates at 1.25 Gbps (typical), providing up to 1 Gbps of data bandwidth over

a copper or optical media interface.

This device supports the defined 10-bit interface (TBI). In the TBI mode, the serializer/deserializer (SERDES)

accepts 10-bit wide 8b/10b parallel encoded data bytes. The parallel data bytes are serialized and transmitted

differentially at PECL-compatible voltage levels. The SERDES extracts clock information from the input serial

stream and deserializes the data, outputting a parallel 10-bit data byte.

A comprehensive series of built-in tests is provided for self-test purposes, including loopback and pseudorandom

binary sequence (PRBS) generation and verification.

The TLK1221 is housed in a high-performance, thermally enhanced, 40-pin QFN package. Use of this package

does not require any special considerations except to note that the pad, which is an exposed die pad on the

bottom of the device, is a metallic thermal and electrical conductor. It is required that the TLK1221 pad be

soldered to the thermal land on the board as it serves as the main ground connection for the device.

The TLK1221 is characterized for operation from –40°C to 85°C.

This device uses a 2.5-V supply. The I/O section is 3.3-V compatible. With the 2.5-V supply, the chipset is very

power-efficient, dissipating less than 200 mW typical power when operating at 1.25 Gbps.

The TLK1221 is designed to be hot-plug capable. A power-on reset causes RBC0, RBC1, the parallel output

signal terminals, TXP, and TXN to be held in the high-impedance state.