FEATURES

· High-Performance Static CMOS Technology

· TMS470R1x 16/32-Bit RISC Core

(ARM7TDMI™)

– 24-MHz System Clock (48-MHz Pipeline

Mode)

– Independent 16/32-Bit Instruction Set

– Open Architecture With Third-Party Support

– Built-In Debug Module

– Big-Endian Format Utilized

· Integrated Memory

– 64K-Byte Program Flash

· One Bank With Five Contiguous Sectors

· Internal State Machine for Programming

and Erase

– 8K-Byte Static RAM (SRAM)

· Operating Features

– Core Supply Voltage (VCC): 1.71 V–2.06 V

– I/O Supply Voltage (VCCIO): 3.0 V–3.6 V

– Low-Power Modes: STANDBY and HALT

– Extended Industrial Temperature Range

· 470+ System Module

– 32-Bit Address Space Decoding

– Bus Supervision for Memory and

Peripherals

– Analog Watchdog (AWD) Timer

– Real-Time Interrupt (RTI)

– System Integrity and Failure Detection

· Zero-Pin Phase-Locked Loop (ZPLL)-Based

Clock Module With Prescaler

– Multiply-by-4 or -8 Internal ZPLL Option

– ZPLL Bypass Mode

· Six Communication Interfaces:

– Two Serial Peripheral Interfaces (SPIs)

· 255 Programmable Baud Rates

– Two Serial Communication Interfaces

(SCIs)

· 224 Selectable Baud Rates

· Asynchronous/Isosynchronous Modes

– Standard CAN Controller (SCC)

– 16-Mailbox Capacity

· Fully Compliant With CAN Protocol,

Version 2.0B

– Class II Serial Interface (C2SIa)

· Two Selectable Data Rates

· Normal Mode 10.4 Kbps and 4X Mode

41.6 Kbps

· High-End Timer (HET)

– 13 Programmable I/O Channels:

· 12 High-Resolution Pins

· 1 Standard-Resolution Pin

– High-Resolution Share Feature (XOR)

– HET RAM (64-Instruction Capacity)

· 10-Bit Multi-Buffered ADC (MibADC)

8-Channel

– 64-Word FIFO Buffer

– Single- or Continuous-Conversion Modes

– 1.55 ms Minimum Sample and Conversion

Time

– Calibration Mode and Self-Test Features

· 6 External Interrupts

· Flexible Interrupt Handling

· 5 Dedicated General-Purpose I/O (GIO) Pins,

1 Input-Only GIO Pin, and 34 Additional

Peripheral I/Os

· External Clock Prescale (ECP) Module

– Programmable Low-Frequency External

Clock (CLK)

· On-Chip Scan-Base Emulation Logic, IEEE

Standard 1149.1 (1) (JTAG) Test-Access Port

· 80-Pin Plastic Low-Profile Quad Flatpack (PN

Suffix)