1FEATURES

23· High-Performance Static CMOS Technology

· TMS470R1x 16/32-Bit RISC Core

(ARM7TDMI™)

– 24-MHz System Clock (48-MHz Pipeline)

– Independent 16/32-Bit Instruction Set

– Open Architecture With Third-Party Support

– Built-In Debug Module

· Integrated Memory

– 384K-Byte Program Flash

– Three Banks With 18 Contiguous

Sectors

– 32K-Byte Static RAM (SRAM)

· Operating Features

– Core Supply Voltage (VCC): 1.71 V to 2.05 V

– I/O Supply Voltage (VCCIO): 3.0 V to 3.6 V

– Low-Power Modes: STANDBY and HALT

– Extended Industrial Temperature Range

· 470+ System Module

– 32-Bit Address Space Decoding

– Bus Supervision for Memory/Peripherals

– Analog Watchdog (AWD) Timer

– Enhanced Real-Time Interrupt (RTI)

– Interrupt Expansion Module (IEM)

– System Integrity and Failure Detection

· Direct Memory Access (DMA) Controller

– 32 Control Packets and 16 Channels

· Zero-Pin Phase-Locked Loop (ZPLL)-Based

Clock Module With Prescaler

– Multiply-by-4 or -8 Internal ZPLL Option

– ZPLL Bypass Mode

· Expansion Bus Module (EBM) (PGE Package)

– Supports 8- and 16-Bit Expansion Bus

Memory Interface Mappings

– 40 I/O Expansion Bus Pins

· Ten Communication Interfaces:

– Two Serial Peripheral Interfaces (SPIs)

– 255 Programmable Baud Rates

– Two Serial Communication Interfaces

(SCIs)

– 224 Selectable Baud Rates

– Asynchronous/Isosynchronous Modes

– Two Standard CAN Controllers (SCC)

– 16-Mailbox Capacity

– Fully Compliant With CAN Protocol,

Version 2.0B

– Class II Serial Interface B (C2SIb)

– Normal 10.4 Kbps and 4X Mode

41.6 Kbps

– Three Inter-Integrated Circuit (I2C) Modules

(See I2C Notes in TMS470R1A384 Silicon

Errata, Literature Number SPNZ148)

– Multi-Master and Slave Interfaces

– Up to 400 Kbps (Fast Mode)

– 7- and 10-Bit Address Capability

· High-End Timer (HET)

– 12 Programmable I/O Channels:

– 12 High-Resolution Pins

– High-Resolution Share Feature (XOR)

– High-End Timer RAM

– 64-Instruction Capacity

· External Clock Prescale (ECP) Module

– Programmable Low-Frequency External

Clock (CLK)

· 12-Channel 10-Bit Multi-Buffered

Analog-to-Digital Converter (MibADC)

– 32-Word FIFO Buffer

– Single- or Continuous-Conversion Modes

– 1.55-μs Minimum Sample/Conversion Time

– Calibration Mode and Self-Test Features

· 55 Dedicated General-Purpose I/O (GIO) Pins

and 39 Additional Peripheral I/Os (PGE)

· 14 Dedicated General-Purpose I/O (GIO) Pins

and 39 Additional Peripheral I/Os (PZ)

· Flexible Interrupt Handling

· Eight External Interrupts

· On-Chip Scan-Base Emulation Logic, IEEE

Standard 1149.1(1) (JTAG) Test-Access Port

· 144-Pin Plastic Low-Profile Quad Flatpack

(PGE Suffix)

· 100-Pin Plastic Low-Profile Quad Flatpack

(PZ Suffix)