Advanced Multibus Architecture With Three

Separate 16-Bit Data Memory Buses and

One Program Memory Bus

40-Bit Arithmetic Logic Unit (ALU)

Including a 40-Bit Barrel Shifter and Two

Independent 40-Bit Accumulators

17-  17-Bit Parallel Multiplier Coupled to a

40-Bit Dedicated Adder for Non-Pipelined

Single-Cycle Multiply/Accumulate (MAC)

Operation

Compare, Select, and Store Unit (CSSU) for

the Add/Compare Selection of the Viterbi

Operator

Exponent Encoder to Compute an

Exponent Value of a 40-Bit Accumulator

Value in a Single Cycle

Two Address Generators With Eight

Auxiliary Registers and Two Auxiliary

Register Arithmetic Units (ARAUs)

Data Bus With a Bus Holder Feature

Address Bus With a Bus Holder Feature

Extended Addressing Mode for 8M  16-Bit

Maximum Addressable External Program

Space

192K  16-Bit Maximum Addressable

Memory Space (64K Words Program,

64K Words Data, and 64K Words I/O)

On-Chip ROM with Some Configurable to

Program/Data Memory

Dual-Access On-Chip RAM

Single-Access On-Chip RAM

Single-Instruction Repeat and

Block-Repeat Operations for Program Code

Block-Memory-Move Instructions for Better

Program and Data Management

Instructions With a 32-Bit Long Word

Operand

Instructions With Two- or Three-Operand

Reads

Arithmetic Instructions With Parallel Store

and Parallel Load

Conditional Store Instructions

Fast Return From Interrupt

On-Chip Peripherals

-- Software-Programmable Wait-State

Generator and Programmable Bank

Switching

-- On-Chip Phase-Locked Loop (PLL) Clock

Generator With Internal Oscillator or

External Clock Source

-- Time-Division Multiplexed (TDM) Serial

Port

-- Buffered Serial Port (BSP)

-- 8-Bit Parallel Host Port Interface (HPI)

-- One 16-Bit Timer

-- External-Input/Output (XIO) Off Control

to Disable the External Data Bus,

Address Bus and Control Signals

Power Consumption Control With IDLE1,

IDLE2, and IDLE3 Instructions With

Power-Down Modes

CLKOUT Off Control to Disable CLKOUT

On-Chip Scan-Based Emulation Logic,

IEEE Std 1149.1† (JTAG) Boundary Scan

Logic

15-ns Single-Cycle Fixed-Point Instruction

Execution Time (66 MIPS) for 3.3-V Power

Supply

12.5-ns Single-Cycle Fixed-Point

Instruction Execution Time (80 MIPS) for

3.3-V Power Supply

description

The TMS320LC548 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’548) is based on

an advanced modified Harvard architecture that has one program memory bus and three data memory buses.

The processor also provides an arithmetic logic unit (ALU) that has a high degree of parallelism,

application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The ’548 also utilizes

a highly specialized instruction set, which is the basis of its operational flexibility and speed.

Separate program and data spaces allow simultaneous access to program instructions and data, providing the

high degree of parallelism. Two reads and one write operation can be performed in a single cycle. Instructions

with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be

transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic,

and bit-manipulation operations that can all be performed in a single machine cycle. In addition, the ’548

includes the control mechanisms to manage interrupts, repeated operations, and function calls.

This data sheet contains the pin layouts, signal descriptions, and electrical specifications for theTMS320VC548

DSP. For additional information, see the TMS320C54x, TMS320LC54x, TMS320VC54x Fixed-Point Digital

Signal Processors data sheet (literature number SPRS039). The SPRS039 is considered a family functional

overview and should be used in conjunction with this data sheet.