位置:SNJ54LS173AFK > SNJ54LS173AFK详情

SNJ54LS173AFK中文资料

厂家型号

SNJ54LS173AFK

文件大小

966.44Kbytes

页面数量

19

功能描述

4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1-Element 20-Pin LCCC Tube

数据手册

下载地址一下载地址二到原厂下载

生产厂商

TI2

SNJ54LS173AFK数据手册规格书PDF详情

3-State Outputs Interface Directly With

System Bus

Gated Output-Control LInes for Enabling or

Disabling the Outputs

Fully Independent Clock Virtually

Eliminates Restrictions for Operating in

One of Two Modes:

– Parallel Load

– Do Nothing (Hold)

For Application as Bus Buffer Registers

Package Options Include Plastic

Small-Outline (D) Packages, Ceramic Flat

(W) Packages, Ceramic Chip Carriers (FK),

and Standard Plastic (N) and Ceramic (J)

DIPs

description

The ’173 and ’LS173A 4-bit registers include

D-type flip-flops featuring totem-pole 3-state

outputs capable of driving highly capacitive

or relatively low-impedance loads. The

high-impedance third state and increased

high-logic-level drive provide these flip-flops with

the capability of being connected directly to and

driving the bus lines in a bus-organized system without need for interface or pull-up components. Up to 128 of

the SN74173 or SN74LS173A outputs can be connected to a common bus and still drive two Series 54/74 or

54LS/74LS TTL normalized loads, respectively. Similarly, up to 49 of the SN54173 or SN54LS173A outputs can

be connected to a common bus and drive one additional Series 54/74 or 54LS/74LS TTL normalized load,

respectively. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic

levels, the output control circuitry is designed so that the average output disable times are shorter than the

average output enable times.

Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When both

data-enable (G1, G2) inputs are low, data at the D inputs are loaded into their respective flip-flops on the next

positive transition of the buffered clock input. Gate output-control (M, N) inputs also are provided. When both

are low, the normal logic states (high or low levels) of the four outputs are available for driving the loads or bus

lines. The outputs are disabled independently from the level of the clock by a high logic level at either

output-control input. The outputs then present a high impedance and neither load nor drive the bus line. Detailed

operation is given in the function table.

The SN54173 and SN54LS173A are characterized for operation over the full military temperature range of

–55°C to 125°C. The SN74173 and SN74LS173A are characterized for operation from 0°C to 70°C.

SNJ54LS173AFK产品属性

  • 类型

    描述

  • 型号

    SNJ54LS173AFK

  • 制造商

    Texas Instruments

  • 功能描述

    Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1-Element 20-Pin LCCC Tube

  • 制造商

    Rochester Electronics LLC

  • 功能描述

    (NO DUAL) QUAD D-TYPE REGISTER(3-STATE) - Bulk

更新时间:2026-2-4 9:18:00
供应商 型号 品牌 批号 封装 库存 备注 价格
TI
三年内
1983
只做原装正品
TI/德州仪器
21+
NA
12820
只做原装,质量保证
TI/德州仪器
22+
N/A
12245
现货,原厂原装假一罚十!
TI(德州仪器)
25+
LCCC20
1476
原装现货,免费供样,技术支持,原厂对接
TI(德州仪器)
24+
-
690000
代理渠道/支持实单/只做原装
24+
N/A
56000
一级代理-主营优势-实惠价格-不悔选择
TI/德州仪器
22+
NA
5750
可订货 请确认
TI/德州仪器
2450+
NA
9850
只做原厂原装正品现货或订货假一赔十!
TI
25+
-
20948
样件支持,可原厂排单订货!
Texas Instruments
24+25+
16500
全新原厂原装现货!受权代理!可送样可提供技术支持!