Wide Operating Voltage Range of 2 V to 6 V

Outputs Can Drive Up To 10 LSTTL Loads

Low Power Consumption, 80-μA Max ICC

Typical tpd = 14 ns

±4-mA Output Drive at 5 V

Low Input Current of 1 μA Max

Full Decoding of Input Logic

All Outputs Are High for Invalid BCD

Conditions

Also for Applications as 3-Line to 8-Line

Decoders

description/ordering information

These decimal decoders consist of eight inverters and ten 4-input NAND gates. The inverters are connected

in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of valid input logic

ensures that all inputs remain off for all invalid input conditions.