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SN75LVDS86ADGG中文资料

厂家型号

SN75LVDS86ADGG

文件大小

518.549Kbytes

页面数量

22

功能描述

FlatLink™ RECEIVER

总线接收器 Flatlink

数据手册

原厂下载下载地址一下载地址二到原厂下载

生产厂商

TI2

SN75LVDS86ADGG数据手册规格书PDF详情

3:21 Data Channel Expansion at up to

178.5 Mbytes/s Throughput

Suited for SVGA, XGA, or SXGA Display

Data Transmission From Controller to

Display With Very Low EMI

Three Data Channels and Clock

Low-Voltage Differential Channels In and

21 Data and Clock Low-Voltage TTL

Channels Out

Operates From a Single 3.3-V Supply

Tolerates 4-kV HBM ESD

Packaged in Thin Shrink Small-Outline

Package (TSSOP) With 20-Mil Terminal

Pitch

Consumes Less Than 1 mW When Disabled

Wide Phase-Lock Input Frequency Range

of 31 MHz to 68 MHz

No External Components Required for PLL

Inputs Meet or Exceed the Standard

Requirements of ANSI EIA/TIA-644

Standard

Improved Replacement for the DS90C364

and SN75LVDS86

Improved Jitter Tolerance

See SN65LVDS86A-Q1 Data Sheet for

Information About the Automotive

Qualified Version

description

The SN65LVDS86A/SN75LVDS86A FlatLink receiver contains three serial-in 7-bit parallel-out shift registers

and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions

allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, ’83, ’84, or ’85, over

four balanced-pair conductors and expansion to 21 bits of single-ended low-voltage LVTTL synchronous data

at a lower transfer rate.

When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input

clock (CLKIN) rate. The data is then unloaded to a 21-bit-wide LVTTL parallel bus at the CLKIN rate. The

’LVDS86A presents valid data on the falling edge of the output clock (CLKOUT).

The ’LVDS86A requires only four line-termination resistors for the differential inputs and little or no control. The

data bus appears the same at the input to the transmitter and output of the receiver with the data transmission

transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN)

active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level

on this signal clears all internal registers to a low level.

The SN75LVDS86A is characterized for operation over ambient free-air temperatures of 0C to 70C. The

SN65LVDS86A is characterized for operation over the full Automotive temperature range of −40°C to 125°C.

SN75LVDS86ADGG产品属性

  • 类型

    描述

  • 型号

    SN75LVDS86ADGG

  • 功能描述

    总线接收器 Flatlink

  • RoHS

  • 制造商

    Texas Instruments

  • 接收机数量

    4

  • 接收机信号类型

    Differential

  • 接口类型

    EIA/TIA-422-B, V.11

  • 工作电源电压

    3.3 V

  • 最大工作温度

    + 85 C

  • 最小工作温度

    - 40 C

  • 封装/箱体

    TSSOP-16

  • 封装

    Reel

更新时间:2025-10-14 16:21:00
供应商 型号 品牌 批号 封装 库存 备注 价格
25+
5000
TI优势分销,原装正品渠道,0755-61337859 朱R QQ1005433625
TI/德州仪器
25+
TSSOP48
12496
TI/德州仪器原装正品SN75LVDS86ADGGR即刻询购立享优惠#长期有货
TI
21+
TSSOP48
90000
全新原装鄙视假货
TI
16+
TSSOP48
32500
全新原装现货供应2
TI/德州仪器
24+
TSSOP48
46
只做原厂渠道 可追溯货源
原厂原包
24+
原装
38560
原装进口现货,工厂客户可以放款。17377264928微信同
TI
2021+
TSSOP48
6800
原厂原装,欢迎咨询
TI(德州仪器)
24+
TSSOP486
935
只做原装,提供一站式配单服务,代工代料。BOM配单
TI
2430+
TSSOP48
8540
只做原装正品假一赔十为客户做到零风险!!
TI
17+
TSSOP
6200
100%原装正品现货

SN75LVDS86ADGGR 价格

参考价格:¥18.4095

型号:SN75LVDS86ADGGR 品牌:TI 备注:这里有SN75LVDS86ADGG多少钱,2025年最近7天走势,今日出价,今日竞价,SN75LVDS86ADGG批发/采购报价,SN75LVDS86ADGG行情走势销售排排榜,SN75LVDS86ADGG报价。