1 Features

1• LVDS Display Series Interfaces Directly to LCD

Display Panels With Integrated LVDS

• Package Options: 4.5-mm x 7-mm BGA, and 8.1-

mm x 14-mm TSSOP

• 1.8-V Up to 3.3-V Tolerant Data Inputs to Connect

Directly to Low-Power, Low-Voltage Application

and Graphic Processors

• Transfer Rate up to 135 Mpps (Mega Pixel Per

Second); Pixel Clock Frequency Range 10 MHz to

135 MHz

• Suited for Display Resolutions Ranging From

HVGA up to HD With Low EMI

• Operates From a Single 3.3-V Supply and 170

mW (Typ.) at 75 MHz

• 28 Data Channels Plus Clock in Low-Voltage TTL

to 4 Data Channels Plus Clock Out Low-Voltage

Differential

• Consumes Less Than 1 mW When Disabled

• Selectable Rising or Falling Clock Edge Triggered

Inputs

• ESD: 5-kV HBM

• Support Spread Spectrum Clocking (SSC)

• Compatible with all OMAP™ 2x, OMAP™ 3x, and

DaVinci™ Application Processors

2 Applications

• LCD Display Panel Driver

• UMPC and Netbook PC

• Digital Picture Frame

3 Description

The SN75LVDS83B FlatLink™ transmitter contains

four 7-bit parallel-load serial-out shift registers, a 7X

clock synthesizer, and five Low-Voltage Differential

Signaling (LVDS) line drivers in a single integrated

circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five

balanced-pair conductors for receipt by a compatible

receiver, such as the SN75LVDS82 and LCD panels

with integrated LVDS receiver.

When transmitting, data bits D0 through D27 are

each loaded into registers upon the edge of the input

clock signal (CLKIN). The rising or falling edge of the

clock can be selected via the clock select (CLKSEL)

pin. The frequency of CLKIN is multiplied seven times, and then used to unload the data registers in

7-bit slices and serially. The four serial streams and a

phase-locked clock (CLKOUT) are then output to

LVDS output drivers. The frequency of CLKOUT is

the same as the input clock, CLKIN.